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From: Peter Maydell <peter.maydell@linaro.org>
To: QEMU Developers <qemu-devel@nongnu.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, Patch Tracking <patches@linaro.org>
Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH 0/7] Fix some more EL3 things and enable EL3 for AArch64
Date: Mon, 8 Feb 2016 13:18:34 +0000	[thread overview]
Message-ID: <CAFEAcA-7s0DCVLH=yHPcY+T=OOFNJedVrHA+t-y8CPYx7j0B6A@mail.gmail.com> (raw)
In-Reply-To: <1454506721-11843-1-git-send-email-peter.maydell@linaro.org>

On 3 February 2016 at 13:38, Peter Maydell <peter.maydell@linaro.org> wrote:
> This series fixes a couple more minor EL3 related missing parts,
> and then turns on EL3 for AArch64 CPUs. The minor fixed things are:
>  * implement MDCR_EL3 and SDCR
>  * trap Secure EL1 accesses to SCR and MVBAR to EL3
>  * add EL3 support to the code that decides whether to generate
>    debug exceptions
>  * fix corner cases in our NSACR handling
>
> To do the NSACR fix I had to change the CPAccessFn API to take
> an extra bool to tell the function if the access is a read or write.
>
> The only major thing I know of that we're missing for 64-bit EL3
> is that we need to go through the "EL3 configurable controls" section
> of the ARM ARM to make sure we trap on the right things. But
> (a) I expect we're missing some for 32-bit as well and (b) this
> is enough to run some real-world EL3 code (ARM Trusted Firmware
> and OP-TEE), so it makes sense to me to turn on EL3 now.

Applied to target-arm.next with some very minor tweaks to patch 2
(add .resetvalue = 0 to the MDCR_EL3 regdef, add a line to the comment.)

thanks
-- PMM

      parent reply	other threads:[~2016-02-08 13:18 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-03 13:38 [Qemu-devel] [PATCH 0/7] Fix some more EL3 things and enable EL3 for AArch64 Peter Maydell
2016-02-03 13:38 ` [Qemu-devel] [PATCH 1/7] target-arm: Fix typo in comment in arm_is_secure_below_el3() Peter Maydell
2016-02-05  9:52   ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2016-02-06 11:49   ` [Qemu-devel] " Edgar E. Iglesias
2016-02-06 18:24   ` [Qemu-devel] [Qemu-arm] " Sergey Fedorov
2016-02-03 13:38 ` [Qemu-devel] [PATCH 2/7] target-arm: Implement MDCR_EL3 and SDCR Peter Maydell
2016-02-05 11:13   ` Alex Bennée
2016-02-05 11:28     ` Peter Maydell
2016-02-06 12:04   ` Edgar E. Iglesias
2016-02-06 18:42   ` Sergey Fedorov
2016-02-08 13:11     ` Peter Maydell
2016-02-03 13:38 ` [Qemu-devel] [PATCH 3/7] target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR Peter Maydell
2016-02-05 13:43   ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2016-02-06 12:17   ` [Qemu-devel] " Edgar E. Iglesias
2016-02-06 13:48     ` Peter Maydell
2016-02-06 16:03       ` Edgar E. Iglesias
2016-02-06 16:10   ` Edgar E. Iglesias
2016-02-03 13:38 ` [Qemu-devel] [PATCH 4/7] target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3 Peter Maydell
2016-02-05 14:09   ` Alex Bennée
2016-02-05 15:55     ` Peter Maydell
2016-02-06 18:43   ` Sergey Fedorov
2016-02-03 13:38 ` [Qemu-devel] [PATCH 5/7] target-arm: Add isread parameter to CPAccessFns Peter Maydell
2016-02-05 14:20   ` Alex Bennée
2016-02-05 14:29     ` Peter Maydell
2016-02-05 16:17       ` Alex Bennée
2016-02-05 16:27         ` Peter Maydell
2016-02-05 16:43           ` Alex Bennée
2016-02-06 16:16   ` Edgar E. Iglesias
2016-02-06 18:52   ` Sergey Fedorov
2016-02-03 13:38 ` [Qemu-devel] [PATCH 6/7] target-arm: Implement NSACR trapping behaviour Peter Maydell
2016-02-05 16:07   ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2016-02-05 16:22     ` Peter Maydell
2016-02-06 16:42   ` [Qemu-devel] " Edgar E. Iglesias
2016-02-03 13:38 ` [Qemu-devel] [PATCH 7/7] target-arm: Enable EL3 for Cortex-A53 and Cortex-A57 Peter Maydell
2016-02-05 16:08   ` Alex Bennée
2016-02-06 16:43   ` Edgar E. Iglesias
2016-02-06 18:55   ` Sergey Fedorov
2016-02-08 13:18 ` Peter Maydell [this message]

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