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Mon, 19 Jul 2021 07:17:22 -0700 (PDT) MIME-Version: 1.0 References: <20210713133726.26842-1-peter.maydell@linaro.org> <20210713133726.26842-9-peter.maydell@linaro.org> In-Reply-To: From: Peter Maydell Date: Mon, 19 Jul 2021 15:16:41 +0100 Message-ID: Subject: Re: [PATCH for-6.2 08/34] target/arm: Fix VPT advance when ECI is non-zero To: Richard Henderson Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 16 Jul 2021 at 17:58, Richard Henderson wrote: > > On 7/13/21 6:37 AM, Peter Maydell wrote: > > if (mask01 > 8) { > > - /* high bit set, but not 0b1000: invert the relevant half of P0 */ > > - vpr ^= 0xff; > > + if (eci == ECI_NONE) { > > + /* high bit set, but not 0b1000: invert the relevant half of P0 */ > > + vpr ^= 0xff; > > + } else if (eci == ECI_A0) { > > + /* Invert only the beat 1 P0 bits, as we didn't execute beat 0 */ > > + vpr ^= 0xf0; > > + } /* otherwise we didn't execute either beat 0 or beat 1 */ > > } > > if (mask23 > 8) { > > - /* high bit set, but not 0b1000: invert the relevant half of P0 */ > > - vpr ^= 0xff00; > > + if (eci != ECI_A0A1A2 && eci != ECI_A0A1A2B0) { > > + /* high bit set, but not 0b1000: invert the relevant half of P0 */ > > + vpr ^= 0xff00; > > + } else { > > + /* We didn't execute beat 2, only invert the beat 3 P0 bits */ > > + vpr ^= 0xf000; > > + } > > } > > It might not be any cleaner, but I wondered if mve_eci_mask could help here. > > inv_mask = mve_eci_mask(...); > if (mask01 <= 8) { > inv_mask &= ~0xff; > } > if (mask23 <= 8) { > inv_mask &= ~0xff00; > } > vpr ^= inv_mask; Yes, I think that works better (you need to capture the ECI mask at the start of the function before we update env->condexec_bits, though). thanks -- PMM