From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:37353)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1aS3E8-0005aH-4u
	for qemu-devel@nongnu.org; Sat, 06 Feb 2016 08:48:40 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1aS3E7-0005u7-7o
	for qemu-devel@nongnu.org; Sat, 06 Feb 2016 08:48:40 -0500
Received: from mail-vk0-x232.google.com ([2607:f8b0:400c:c05::232]:33770)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1aS3E7-0005tu-3i
	for qemu-devel@nongnu.org; Sat, 06 Feb 2016 08:48:39 -0500
Received: by mail-vk0-x232.google.com with SMTP id k196so5678086vka.0
	for <qemu-devel@nongnu.org>; Sat, 06 Feb 2016 05:48:38 -0800 (PST)
MIME-Version: 1.0
In-Reply-To: <20160206121756.GC3913@toto>
References: <1454506721-11843-1-git-send-email-peter.maydell@linaro.org>
	<1454506721-11843-4-git-send-email-peter.maydell@linaro.org>
	<20160206121756.GC3913@toto>
From: Peter Maydell <peter.maydell@linaro.org>
Date: Sat, 6 Feb 2016 13:48:19 +0000
Message-ID: <CAFEAcA-KxmVhGxk4d=+yMj5+NxCaPeGNc_3m4guB3Y72hSMcDg@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Subject: Re: [Qemu-devel] [PATCH 3/7] target-arm: Use
	access_trap_aa32s_el1() for SCR and MVBAR
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>, Patch Tracking <patches@linaro.org>

On 6 February 2016 at 12:17, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> It seems to me like if EL3 is running in AArch32, then we shouldn't
> trap accesses from Secure EL1 but I can't find that logic. Am I missing
> something?

If EL3 is running in AArch32 then there is no Secure EL1 -- all
of SVC, IRQ, and the other PL1 modes run at EL3 privilege,
and arm_current_el() will return 3 in this situation.

thanks
-- PMM