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* [Qemu-devel] [PULL 00/29] target-arm queue
@ 2019-08-16 13:16 Peter Maydell
  2019-08-16 13:16 ` [Qemu-devel] [PULL 01/29] target/arm: generate a custom MIDR for -cpu max Peter Maydell
                   ` (29 more replies)
  0 siblings, 30 replies; 33+ messages in thread
From: Peter Maydell @ 2019-08-16 13:16 UTC (permalink / raw)
  To: qemu-devel

First arm pullreq of 4.2...

thanks
-- PMM

The following changes since commit 27608c7c66bd923eb5e5faab80e795408cbe2b51:

  Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20190814a' into staging (2019-08-16 12:00:18 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190816

for you to fetch changes up to 664b7e3b97d6376f3329986c465b3782458b0f8b:

  target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word (2019-08-16 14:02:53 +0100)

----------------------------------------------------------------
target-arm queue:
 * target/arm: generate a custom MIDR for -cpu max
 * hw/misc/zynq_slcr: refactor to use standard register definition
 * Set ENET_BD_BDU in I.MX FEC controller
 * target/arm: Fix routing of singlestep exceptions
 * refactor a32/t32 decoder handling of PC
 * minor optimisations/cleanups of some a32/t32 codegen
 * target/arm/cpu64: Ensure kvm really supports aarch64=off
 * target/arm/cpu: Ensure we can use the pmu with kvm
 * target/arm: Minor cleanups preparatory to KVM SVE support

----------------------------------------------------------------
Aaron Hill (1):
      Set ENET_BD_BDU in I.MX FEC controller

Alex Bennée (1):
      target/arm: generate a custom MIDR for -cpu max

Andrew Jones (6):
      target/arm/cpu64: Ensure kvm really supports aarch64=off
      target/arm/cpu: Ensure we can use the pmu with kvm
      target/arm/helper: zcr: Add build bug next to value range assumption
      target/arm/cpu: Use div-round-up to determine predicate register array size
      target/arm/kvm64: Fix error returns
      target/arm/kvm64: Move the get/put of fpsimd registers out

Damien Hedde (1):
      hw/misc/zynq_slcr: use standard register definition

Peter Maydell (2):
      target/arm: Factor out 'generate singlestep exception' function
      target/arm: Fix routing of singlestep exceptions

Richard Henderson (18):
      target/arm: Pass in pc to thumb_insn_is_16bit
      target/arm: Introduce pc_curr
      target/arm: Introduce read_pc
      target/arm: Introduce add_reg_for_lit
      target/arm: Remove redundant s->pc & ~1
      target/arm: Replace s->pc with s->base.pc_next
      target/arm: Replace offset with pc in gen_exception_insn
      target/arm: Replace offset with pc in gen_exception_internal_insn
      target/arm: Remove offset argument to gen_exception_bkpt_insn
      target/arm: Use unallocated_encoding for aarch32
      target/arm: Remove helper_double_saturate
      target/arm: Use tcg_gen_extract_i32 for shifter_out_im
      target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB
      target/arm: Remove redundant shift tests
      target/arm: Use ror32 instead of open-coding the operation
      target/arm: Use tcg_gen_rotri_i32 for gen_swap_half
      target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR
      target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word

 target/arm/cpu.h               |  13 +-
 target/arm/helper.h            |   1 -
 target/arm/kvm_arm.h           |  28 ++
 target/arm/translate-a64.h     |   4 +-
 target/arm/translate.h         |  39 ++-
 hw/misc/zynq_slcr.c            | 450 ++++++++++++++++----------------
 hw/net/imx_fec.c               |   4 +
 target/arm/cpu.c               |  30 ++-
 target/arm/cpu64.c             |  31 ++-
 target/arm/helper.c            |   7 +
 target/arm/kvm.c               |   7 +
 target/arm/kvm64.c             | 161 +++++++-----
 target/arm/op_helper.c         |  15 --
 target/arm/translate-a64.c     | 130 ++++------
 target/arm/translate-vfp.inc.c |  45 +---
 target/arm/translate.c         | 572 +++++++++++++++++------------------------
 16 files changed, 771 insertions(+), 766 deletions(-)


^ permalink raw reply	[flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 00/29] target-arm queue
@ 2014-02-08 15:57 Peter Maydell
  2014-02-11 11:59 ` Peter Maydell
  0 siblings, 1 reply; 33+ messages in thread
From: Peter Maydell @ 2014-02-08 15:57 UTC (permalink / raw)
  To: Anthony Liguori; +Cc: Blue Swirl, qemu-devel, Aurelien Jarno

Pull request for the target-arm queue...

thanks
-- PMM

The following changes since commit 3ea3bd62451ac79478b440ad9fe2a4cd69783a1f:

  Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20140204-1' into staging (2014-02-08 13:12:50 +0000)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140208

for you to fetch changes up to 69991d7dcbcf7f3fe38274bc67fcba3cbbfda0cf:

  arm/zynq: Add software system reset via SCLR (2014-02-08 14:50:48 +0000)

----------------------------------------------------------------
target-arm queue:
 * more A64 Neon instructions
 * AArch32 VCVTB and VCVTT ARMv8 instructions
 * fixes to inaccuracies in GIC emulation
 * libvixl disassembler for A64
 * Allwinner SoC ethernet controller
 * zynq software system reset support

----------------------------------------------------------------
Alex Bennée (1):
      target-arm: A64: Add 2-reg-misc REV* instructions

Beniamino Galvani (4):
      util/fifo8: implement push/pop of multiple bytes
      util/fifo8: clear fifo head upon reset
      hw/net: add support for Allwinner EMAC Fast Ethernet controller
      hw/arm/allwinner-a10: initialize EMAC

Christoffer Dall (5):
      arm_gic: Fix GIC pending behavior
      arm_gic: Keep track of SGI sources
      arm_gic: Support setting/getting binary point reg
      vmstate: Add uint32 2D-array support
      arm_gic: Add GICC_APRn state to the GICState

Claudio Fontana (1):
      disas: Implement disassembly output for A64

Peter Maydell (16):
      target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns
      target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns
      target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD
      tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR
      target-arm: A64: Implement scalar pairwise ops
      target-arm: A64: Implement remaining integer scalar-3-same insns
      target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc
      target-arm: A64: Add skeleton decode for SIMD 2-reg misc group
      target-arm: A64: Implement 2-register misc compares, ABS, NEG
      target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
      target-arm: A64: Add narrowing 2-reg-misc instructions
      target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group
      rules.mak: Support .cc as a C++ source file suffix
      rules.mak: Link with C++ if we have a C++ compiler
      disas: Add subset of libvixl sources for A64 disassembler
      disas/libvixl: Fix upstream libvixl compilation issues

Sebastian Huber (1):
      arm/zynq: Add software system reset via SCLR

Will Newton (1):
      target-arm: Add support for AArch32 64bit VCVTB and VCVTT

 configure                             |    4 +
 default-configs/arm-softmmu.mak       |    1 +
 disas.c                               |   14 +-
 disas/Makefile.objs                   |    5 +
 disas/arm-a64.cc                      |   87 ++
 disas/libvixl/LICENCE                 |   30 +
 disas/libvixl/Makefile.objs           |    8 +
 disas/libvixl/README                  |   12 +
 disas/libvixl/a64/assembler-a64.h     | 1784 +++++++++++++++++++++++++++++++++
 disas/libvixl/a64/constants-a64.h     | 1104 ++++++++++++++++++++
 disas/libvixl/a64/cpu-a64.h           |   56 ++
 disas/libvixl/a64/decoder-a64.cc      |  712 +++++++++++++
 disas/libvixl/a64/decoder-a64.h       |  198 ++++
 disas/libvixl/a64/disasm-a64.cc       | 1678 +++++++++++++++++++++++++++++++
 disas/libvixl/a64/disasm-a64.h        |  109 ++
 disas/libvixl/a64/instructions-a64.cc |  238 +++++
 disas/libvixl/a64/instructions-a64.h  |  344 +++++++
 disas/libvixl/globals.h               |   65 ++
 disas/libvixl/platform.h              |   43 +
 disas/libvixl/utils.cc                |  120 +++
 disas/libvixl/utils.h                 |  126 +++
 hw/arm/allwinner-a10.c                |   16 +
 hw/arm/cubieboard.c                   |   11 +-
 hw/intc/arm_gic.c                     |  179 +++-
 hw/intc/arm_gic_common.c              |    8 +-
 hw/intc/gic_internal.h                |   16 +-
 hw/misc/zynq_slcr.c                   |    5 +
 hw/net/Makefile.objs                  |    1 +
 hw/net/allwinner_emac.c               |  539 ++++++++++
 include/disas/bfd.h                   |    1 +
 include/hw/arm/allwinner-a10.h        |    3 +
 include/hw/intc/arm_gic_common.h      |   33 +
 include/hw/net/allwinner_emac.h       |  210 ++++
 include/migration/vmstate.h           |    6 +
 include/qemu/fifo8.h                  |   61 ++
 rules.mak                             |   14 +-
 target-arm/helper.h                   |    1 +
 target-arm/neon_helper.c              |   12 +
 target-arm/translate-a64.c            | 1213 ++++++++++++++++++++--
 target-arm/translate.c                |   83 +-
 tcg/tcg.h                             |    3 +
 util/fifo8.c                          |   47 +
 42 files changed, 9044 insertions(+), 156 deletions(-)
 create mode 100644 disas/arm-a64.cc
 create mode 100644 disas/libvixl/LICENCE
 create mode 100644 disas/libvixl/Makefile.objs
 create mode 100644 disas/libvixl/README
 create mode 100644 disas/libvixl/a64/assembler-a64.h
 create mode 100644 disas/libvixl/a64/constants-a64.h
 create mode 100644 disas/libvixl/a64/cpu-a64.h
 create mode 100644 disas/libvixl/a64/decoder-a64.cc
 create mode 100644 disas/libvixl/a64/decoder-a64.h
 create mode 100644 disas/libvixl/a64/disasm-a64.cc
 create mode 100644 disas/libvixl/a64/disasm-a64.h
 create mode 100644 disas/libvixl/a64/instructions-a64.cc
 create mode 100644 disas/libvixl/a64/instructions-a64.h
 create mode 100644 disas/libvixl/globals.h
 create mode 100644 disas/libvixl/platform.h
 create mode 100644 disas/libvixl/utils.cc
 create mode 100644 disas/libvixl/utils.h
 create mode 100644 hw/net/allwinner_emac.c
 create mode 100644 include/hw/net/allwinner_emac.h

^ permalink raw reply	[flat|nested] 33+ messages in thread

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Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-16 13:16 [Qemu-devel] [PULL 00/29] target-arm queue Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 01/29] target/arm: generate a custom MIDR for -cpu max Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 02/29] hw/misc/zynq_slcr: use standard register definition Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 03/29] Set ENET_BD_BDU in I.MX FEC controller Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 04/29] target/arm: Factor out 'generate singlestep exception' function Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 05/29] target/arm: Fix routing of singlestep exceptions Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 06/29] target/arm: Pass in pc to thumb_insn_is_16bit Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 07/29] target/arm: Introduce pc_curr Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 08/29] target/arm: Introduce read_pc Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 09/29] target/arm: Introduce add_reg_for_lit Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 10/29] target/arm: Remove redundant s->pc & ~1 Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 11/29] target/arm: Replace s->pc with s->base.pc_next Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 12/29] target/arm: Replace offset with pc in gen_exception_insn Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 13/29] target/arm: Replace offset with pc in gen_exception_internal_insn Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 14/29] target/arm: Remove offset argument to gen_exception_bkpt_insn Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 15/29] target/arm: Use unallocated_encoding for aarch32 Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 16/29] target/arm: Remove helper_double_saturate Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 17/29] target/arm/cpu64: Ensure kvm really supports aarch64=off Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 18/29] target/arm/cpu: Ensure we can use the pmu with kvm Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 19/29] target/arm/helper: zcr: Add build bug next to value range assumption Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 20/29] target/arm/cpu: Use div-round-up to determine predicate register array size Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 21/29] target/arm/kvm64: Fix error returns Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 22/29] target/arm/kvm64: Move the get/put of fpsimd registers out Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 23/29] target/arm: Use tcg_gen_extract_i32 for shifter_out_im Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 24/29] target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 25/29] target/arm: Remove redundant shift tests Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 26/29] target/arm: Use ror32 instead of open-coding the operation Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 27/29] target/arm: Use tcg_gen_rotri_i32 for gen_swap_half Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 28/29] target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 29/29] target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word Peter Maydell
2019-08-16 17:02 ` [Qemu-devel] [PULL 00/29] target-arm queue Peter Maydell
  -- strict thread matches above, loose matches on Subject: below --
2014-02-08 15:57 Peter Maydell
2014-02-11 11:59 ` Peter Maydell

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