From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9608C433DB for ; Fri, 12 Feb 2021 13:53:43 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5933C64E57 for ; Fri, 12 Feb 2021 13:53:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5933C64E57 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:50536 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAYtC-0004Ia-A0 for qemu-devel@archiver.kernel.org; Fri, 12 Feb 2021 08:53:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49922) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lAYrY-0002lQ-5V for qemu-devel@nongnu.org; Fri, 12 Feb 2021 08:52:01 -0500 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]:43195) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lAYrW-0005wN-2F for qemu-devel@nongnu.org; Fri, 12 Feb 2021 08:51:59 -0500 Received: by mail-ed1-x535.google.com with SMTP id v7so10884119eds.10 for ; Fri, 12 Feb 2021 05:51:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=WqCiZKf/bOd743/BAXPwMMt1kMi3GtNVDcGv11sQawY=; b=n8J29OrXolZflrfy2iZUoY3YoeJrFi6k0d34vfGicQN2P42oefyNhoNO+6szMJODEX m9zZTzHrjBrUpnJfSfKPjmGG/vWtEXiXN76G3c1Tu4GkktQQuYGUMyMg81/kDC+qQEPo Ma+NuXiCK8VKYuailRdx1T5dDP8WVUMQf9RWUMsajgq5d9jIJgVPbcAVVo8toqS1pfQU cNMWOgb7g7KRg+rzRi10kFIzdgTDb12Mdduh4tO1BRdYtZWtS5tOFevdUxvW+6bDRb62 bMDNi2B720OUeRxG+NYxeMT3ve5WswdC52oGWiRkbidzn92aT+On5frHdxdTuzDiQ6YU GzaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to; bh=WqCiZKf/bOd743/BAXPwMMt1kMi3GtNVDcGv11sQawY=; b=StT1sRbaiMNU+Twk/fckwzasZ+Tmn3XeTtUj3i+d8igE+ywSRKyesv6I8xHRDtypJe lZ+tlQ6KcgmMneTgK2o80lqFxCekCHUKxlBIQqEntiAVjbfZ9LJW2B9F48CRMjT/QTso H0av/qk0FH9hYD9O420TCh2FrMsxY7T9YornGPVVqn1OUf9VyPh2yYbZvlZy/HIxv57Q ng4PXZjFA22RyKuHPkmxx1rY5Bd+Nr84XpU70q5x91LEaUDwq7zDIs1OIFyuncRkWDIA 73b6WnR53yPzChs+qsJt4gfIEh6MK7t9IDwhnsIUds4wR5ZJJTSy2ZWvq+9rMJgYszVZ qbPA== X-Gm-Message-State: AOAM530X3QsU+4eunClEZ/PpGXFQuJtwtT6w6/4iNsi6ApZuFqE2Q4Bl ywJLxaYEjk5EAKoXRXxorlPmTCMuU2FKf4MlfMrl+A== X-Google-Smtp-Source: ABdhPJyEfVWBdfEjs+V9VSEM9zGc/Tnxw8wEyBK0rZDp8TGdCMnKStsgj6B9Gkz7KlRusKm/t0lwgAiNkdXbfrVArcE= X-Received: by 2002:a05:6402:3494:: with SMTP id v20mr3589598edc.146.1613137915610; Fri, 12 Feb 2021 05:51:55 -0800 (PST) MIME-Version: 1.0 References: <20210205170019.25319-1-peter.maydell@linaro.org> <20210205170019.25319-8-peter.maydell@linaro.org> In-Reply-To: <20210205170019.25319-8-peter.maydell@linaro.org> From: Peter Maydell Date: Fri, 12 Feb 2021 13:51:44 +0000 Message-ID: Subject: Re: [PATCH 07/24] hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board To: qemu-arm , QEMU Developers Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 5 Feb 2021 at 17:00, Peter Maydell wrote: > > Set the FPGAIO num-leds and have-switches properties explicitly > per-board, rather than relying on the defaults. The AN505 and AN521 > both have the same settings as the default values, but the AN524 will > be different. > > Signed-off-by: Peter Maydell Followon from the update to the previous patch, trivial rename to squash in: diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 94618ae54d2..6e345cf1f09 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -80,7 +80,7 @@ struct MPS2TZMachineClass { uint32_t len_oscclk; const uint32_t *oscclk; uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ - bool fpgaio_switches; /* Does FPGAIO have SWITCH register? */ + bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ const char *armsse_type; }; @@ -247,7 +247,7 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); - qdev_prop_set_bit(DEVICE(fpgaio), "have-switches", mmc->fpgaio_switches); + qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches); sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); } @@ -693,7 +693,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->oscclk = an505_oscclk; mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds = 2; - mmc->fpgaio_switches = false; + mmc->fpgaio_has_switches = false; mmc->armsse_type = TYPE_IOTKIT; } @@ -713,7 +713,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds = 2; - mmc->fpgaio_switches = false; + mmc->fpgaio_has_switches = false; mmc->armsse_type = TYPE_SSE200; } thanks -- PMM