From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Cc: Rebecca Cran <rebecca@nuviainc.com>
Subject: Re: [PATCH] target/arm: Flush correct TLBs in tlbi_aa64_vae2is_write()
Date: Tue, 20 Apr 2021 13:32:39 +0100 [thread overview]
Message-ID: <CAFEAcA-q2paH4Cf6SbvMTN6TvQGEK5UPSZ5tYoPgPneYH-3z=Q@mail.gmail.com> (raw)
In-Reply-To: <20210420123106.10861-1-peter.maydell@linaro.org>
On Tue, 20 Apr 2021 at 13:31, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> In tlbi_aa64_vae2is_write() the calculation
> bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2,
> pageaddr)
>
> has the two arms of the ?: expression reversed. Fix the bug.
>
> Fixes: b6ad6062f1e5
> Reported-by: Rebecca Cran <rebecca@nuviainc.com>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 seconds after sending this I realized that the subject isn't right:
we flush the correct TLBs, but we might consider the wrong number of
bits in the page address to be significant if the TBI enable/disable
state is different for SEL2 and NSEL2. Better subject:
target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write()
thanks
-- PMM
next prev parent reply other threads:[~2021-04-20 12:35 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-20 12:31 [PATCH] target/arm: Flush correct TLBs in tlbi_aa64_vae2is_write() Peter Maydell
2021-04-20 12:32 ` Peter Maydell [this message]
2021-04-20 12:38 ` Philippe Mathieu-Daudé
2021-04-20 13:42 ` Rémi Denis-Courmont
2021-04-20 13:48 ` Rebecca Cran
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