From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46185) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWWPi-00020G-L0 for qemu-devel@nongnu.org; Thu, 18 Feb 2016 16:47:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aWWPh-0004T5-ND for qemu-devel@nongnu.org; Thu, 18 Feb 2016 16:47:06 -0500 Received: from mail-vk0-x235.google.com ([2607:f8b0:400c:c05::235]:33198) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWWPh-0004T1-Hb for qemu-devel@nongnu.org; Thu, 18 Feb 2016 16:47:05 -0500 Received: by mail-vk0-x235.google.com with SMTP id k196so58087453vka.0 for ; Thu, 18 Feb 2016 13:47:05 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <56C62EDA.3010307@tribudubois.net> References: <4499d69ec1326c07481e9d8178e64b63f9748706.1454967766.git.jcd@tribudubois.net> <56C38B52.7080904@tribudubois.net> <56C398FA.8010204@tribudubois.net> <56C62EDA.3010307@tribudubois.net> From: Peter Maydell Date: Thu, 18 Feb 2016 21:46:45 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jean-Christophe DUBOIS Cc: QEMU Developers , Peter Crosthwaite On 18 February 2016 at 20:51, Jean-Christophe DUBOIS wrote: > Le 16/02/2016 22:57, Peter Maydell a =C3=A9crit : > > On 16 February 2016 at 21:47, Jean-Christophe DUBOIS > wrote: > > In QEMU, other Cortex A9 (Versatilepb.c, Exynos, Zynq ...) are also setti= ng > has_el3 to false ... > > So these generally are the "legacy" platforms which were > added before we ever had EL3 support in QEMU. For them it's hard > to turn the EL3 support on for the board even if in theory > it ought to be on, because we don't know what users are > running on it that we might break. With a new to QEMU board > we have an opportunity to get it right from the start. > > > OK, so is the "highbank" the only Qemu Cortex A9 board supporting > el3 yet? Yep. We don't have many A9 boards and most of those we do have are in the 'legacy' bucket. > -kernel I would expect to work, though, at least if the > only issue is the interrupt controller setup. It seems > worth investigating why it goes wrong. > > > Well, I can boot uniprocessor (-smp 1) without trouble but if I turn logs= on > (guest_errors,unimp) I am getting a lot of > > gic_dist_writeb: Bad offset 38x (a few at startup) > Ignoring attempt to switch CPSR_A flag from non-secure world with > SCR.AW bit clear (a lot) > Ignoring attempt to switch CPSR_F flag from non-secure world with > SCR.FW bit clear (a few) This would only be a problem if your kernel needed to use FIQ, I think. > I am not sure if this is a problem. Do you have some opinion on this? > > When I turn SMP (-smp 2 or more), I am unable to complete the boot. As so= on > as my secondary cpu is started QEMU will continue to boot "very slowly" b= ut > doesn't get to the linux user prompt overnight. Does SMP work with EL3 not enabled, or is this a different bug? thanks -- PMM