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Thu, 15 Apr 2021 10:35:08 -0700 (PDT) MIME-Version: 1.0 References: <20210218094706.23038-1-alex.bennee@linaro.org> <20210218094706.23038-19-alex.bennee@linaro.org> <87blaflit2.fsf@linaro.org> <6597cb54-44d9-0798-0786-098286001fe0@kaod.org> In-Reply-To: <6597cb54-44d9-0798-0786-098286001fe0@kaod.org> From: Peter Maydell Date: Thu, 15 Apr 2021 18:34:21 +0100 Message-ID: Subject: Re: [EXTERNAL] Re: [PULL 18/23] accel/tcg: re-factor non-RAM execution code To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , QEMU Developers , qemu-arm , Paolo Bonzini , =?UTF-8?B?QWxleCBCZW5uw6ll?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, 15 Apr 2021 at 18:18, C=C3=A9dric Le Goater wrote: > > On 4/15/21 5:55 PM, Philippe Mathieu-Daud=C3=A9 wrote: > > On 4/15/21 4:54 PM, Peter Maydell wrote: > >> On Thu, 15 Apr 2021 at 15:32, Alex Benn=C3=A9e wrote: > >>> --8<---------------cut here---------------start------------->8--- > >>> accel/tcg: avoid re-translating one-shot instructions > >>> > >>> By definition a single instruction is capable of being an IO > >>> instruction. This avoids a problem of triggering a cpu_io_recompile o= n > >>> a non-cached translation which would only do exactly this anyway. > >>> > >>> Signed-off-by: Alex Benn=C3=A9e > >>> > >>> 1 file changed, 1 insertion(+), 1 deletion(-) > >>> accel/tcg/translate-all.c | 2 +- > >>> > >>> modified accel/tcg/translate-all.c > >>> @@ -1863,7 +1863,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, > >>> > >>> if (phys_pc =3D=3D -1) { > >>> /* Generate a one-shot TB with 1 insn in it */ > >>> - cflags =3D (cflags & ~CF_COUNT_MASK) | 1; > >>> + cflags =3D (cflags & ~CF_COUNT_MASK) | CF_LAST_IO | 1; > >>> } > >>> > >>> max_insns =3D cflags & CF_COUNT_MASK; > >>> --8<---------------cut here---------------end--------------->8--- > >> > >> Yes, this fixes the problem. Do we want to put this in for 6.0? My > >> feeling is that executing from non-RAM is pretty niche, so maybe > >> if we need an rc4 anyway, but this isn't important enough to cause an > >> rc4 itself. > > > > Isn't it the default for Aspeed machines (with U-Boot)? (Cc'ing C=C3=A9= dric). > > You need to set the 'execute-in-place' machine option to load/execute the > instructions from the AHB window of CE0. It's not on by default because > boot can be really slow with some recent u-boot which heavily trash the T= Bs. > > But this seems to work fine with -rc3. Triggering the bug requires both execute-in-place and -icount -- did you test with -icount enabled? thanks -- PMM