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From: Peter Maydell <peter.maydell@linaro.org>
Date: Tue, 1 Mar 2016 16:19:59 +0000
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Subject: Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.
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To: Jean-Christophe DUBOIS <jcd@tribudubois.net>
Cc: QEMU Developers <qemu-devel@nongnu.org>, Peter Crosthwaite <crosthwaite.peter@gmail.com>

On 29 February 2016 at 21:32, Jean-Christophe DUBOIS
<jcd@tribudubois.net> wrote:
> Le 29/02/2016 22:14, Peter Maydell a =C3=A9crit :
>> Is there a datasheet available for this?

> Well the SRC device is described in the i.MX6 reference manual.
>
> http://cache.nxp.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf?fpsp=3D1&WT_=
TYPE=3DReference%20Manuals&WT_VENDOR=3DFREESCALE&WT_FILE_FORMAT=3Dpdf&WT_AS=
SET=3DDocumentation&fileExt=3D.pdf

Thanks for the link.

> I believe it is hardware based. Now it might involve some of the function=
s
> of the internal ROM in the process but we cannot change this behavior in =
any
> way.

The datasheet is pretty clear -- registers like the SRC_GPR<n> are just
"holds some state" registers, and when the system reset controller starts
a secondary CPU it runs through some boot ROM code which reads the
GPR controlling the start address and branches to it.

This means the code you have in the SRC emulation is actually implementing
a combination of the SRC hardware and the boot ROM software. That's OK,
but we should have a comment somewhere that makes it clear that that's
what's going on.

(it is possible to implement the "jump to address as per register" as
code that runs in the guest; highbank has a variant on this. It doesn't
really seem necessary here though.)

On the "secure vs nonsecure" question, I'm not completely sure but I
think that the answer is that it will boot in secure. So we should
use the patche that adds "sabrelite_binfo.secure_boot =3D true;" to the
board code.

thanks
-- PMM