From: Peter Maydell <peter.maydell@linaro.org>
To: Joel Stanley <joel@jms.id.au>
Cc: "Andrew Jeffery" <andrew@aj.id.au>,
qemu-arm <qemu-arm@nongnu.org>, "Cédric Le Goater" <clg@kaod.org>,
"QEMU Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v2] aspeed: Link SCU to the watchdog
Date: Mon, 1 Jul 2019 14:36:06 +0100 [thread overview]
Message-ID: <CAFEAcA93PEEsp-6Ko_ELU+0QYPuYQFJLzX1LT+5+LdPjh-jq+A@mail.gmail.com> (raw)
In-Reply-To: <20190621065242.32535-1-joel@jms.id.au>
On Fri, 21 Jun 2019 at 07:52, Joel Stanley <joel@jms.id.au> wrote:
>
> The ast2500 uses the watchdog to reset the SDRAM controller. This
> operation is usually performed by u-boot's memory training procedure,
> and it is enabled by setting a bit in the SCU and then causing the
> watchdog to expire. Therefore, we need the watchdog to be able to
> access the SCU's register space.
>
> This causes the watchdog to not perform a system reset when the bit is
> set. In the future it could perform a reset of the SDMC model.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> v2: rebase on upstream, rework commit message
Applied to target-arm.next, thanks.
-- PMM
prev parent reply other threads:[~2019-07-01 14:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-21 6:52 [Qemu-devel] [PATCH v2] aspeed: Link SCU to the watchdog Joel Stanley
2019-06-21 8:25 ` Cédric Le Goater
2019-06-21 9:06 ` Philippe Mathieu-Daudé
2019-06-25 6:47 ` Joel Stanley
2019-07-01 13:36 ` Peter Maydell [this message]
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