From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81CA0C433F5 for ; Wed, 18 May 2022 10:33:54 +0000 (UTC) Received: from localhost ([::1]:49480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nrH04-00044D-49 for qemu-devel@archiver.kernel.org; Wed, 18 May 2022 06:33:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42468) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nrGxA-0002YK-DP for qemu-devel@nongnu.org; Wed, 18 May 2022 06:30:52 -0400 Received: from mail-yb1-xb2d.google.com ([2607:f8b0:4864:20::b2d]:37762) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nrGx8-0001Ag-QK for qemu-devel@nongnu.org; Wed, 18 May 2022 06:30:52 -0400 Received: by mail-yb1-xb2d.google.com with SMTP id v71so2898378ybi.4 for ; Wed, 18 May 2022 03:30:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=6VYjo6D60ICm1Bsii96igdB78MhM+JPiWL5ypQJWn0I=; b=kg6uMKZ8PYSzzl/jtgWmPF1BstnjO3j4CwHCu0yKtJQy8oJCXs/O3+J2/Y5R3snvNi xJloCqV5gstk2dp8T//JI31ii1cOBlHI7+m/xH/KiRw7jLMWXxlik3Rtspt/NO91yc4y FX2U5KKqvzOJ7Stp5QzTs59nQci/u0LjCEsosgRsTG+hacBUzftXpDYrmQ0UfHvbqkNF Okj5DsgzvN8gTuAYS0vrlACH6H45ByxEnpAhI4YC51LTKq5F/wDfLYkxvqpRMTqXcfgk kPf8s1dSzUQjCM4DbDpgOn1oqQAfEVbEJvrBQ9QzQcw9ND/ukuCi48bcIr5w56Xs0mWW y/bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6VYjo6D60ICm1Bsii96igdB78MhM+JPiWL5ypQJWn0I=; b=4jVHjltXGI5hGqto+u81NMWvt7dUSCmM8AWQxGHAkL70iWagcG3+Mm2u3O83YTcHQ8 brNoBFce6o4+NgN3ePQg14qa+iSbk5S0aR6gaxIJn43SfaNHMuSn8kwDWMS+6SUYBxjg LuuflmjV+cg3jhYWVeZmh160N7FviiUQ9aqSsVb54eNRzspdPDx5HLxnJUKH6g8flSek EfrIix/yhwQzndFYQ82DL1TZ1TKJW2Gu1aDDV13SnAPOaHqQSqrivioEjlXzUhua1Rkd TU96W3PY8kPuLCOl+gYWB0GO4Ccw6v2uTtS4yQzICDieUTeh7G7MaqRmjo5moxYbTEaz W/3w== X-Gm-Message-State: AOAM5327fS6JQ9xmE2sMT9T4b/X8EyAdyWqbq4hfxXltisSnBLXr0aAG XtmJ4vB2Ege3qVg9XP6/d584tqcaEyoreVle3Y/BhA== X-Google-Smtp-Source: ABdhPJwo1r9S0IGK+pJQaPGkfyAuLx6mIZvjrk5TsYPoAj5DWpq7XkSIqGnM4jNpZZf4gxZD+bfA96zlOobty4SApmE= X-Received: by 2002:a05:6902:1543:b0:649:3124:b114 with SMTP id r3-20020a056902154300b006493124b114mr26435231ybu.39.1652869849850; Wed, 18 May 2022 03:30:49 -0700 (PDT) MIME-Version: 1.0 References: <20220513122852.4063586-1-peter.maydell@linaro.org> In-Reply-To: From: Peter Maydell Date: Wed, 18 May 2022 11:30:38 +0100 Message-ID: Subject: Re: [PATCH] target/arm: Make number of counters in PMCR follow the CPU To: "ishii.shuuichir@fujitsu.com" Cc: =?UTF-8?B?QWxleCBCZW5uw6ll?= , Itaru Kitayama , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b2d; envelope-from=peter.maydell@linaro.org; helo=mail-yb1-xb2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, 18 May 2022 at 00:24, ishii.shuuichir@fujitsu.com wrote: > > Hi, Peter. > > > Shuuichirou, Itaru: this is another patch where we need to know > > an A64FX register value... > > Sorry for the late reply. > > The initial value of the pmcr_el0 register in A64FX is 0x46014040. > > After applying this Peter's patch, should we submit a new patch as a64fx patch from us? > or do you want to fix your own modifications to the patch that peter has posted? > Which is the best procedure? Thanks for looking up the a64fx register value. You don't need to do anything more -- I'll fix up the TODO comment and put the right value into this patch, either when I post a v2 of it or else when I apply it to target-arm.next. -- PMM