From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41920) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aS9LU-0005OL-Nf for qemu-devel@nongnu.org; Sat, 06 Feb 2016 15:20:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aS9LT-0003OS-To for qemu-devel@nongnu.org; Sat, 06 Feb 2016 15:20:40 -0500 Received: from mail-vk0-x22f.google.com ([2607:f8b0:400c:c05::22f]:35607) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aS9LT-0003OG-Jr for qemu-devel@nongnu.org; Sat, 06 Feb 2016 15:20:39 -0500 Received: by mail-vk0-x22f.google.com with SMTP id e6so75304776vkh.2 for ; Sat, 06 Feb 2016 12:20:39 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <56B65289.2090103@tribudubois.net> References: <1453844704-26469-1-git-send-email-jcd@tribudubois.net> <56B65289.2090103@tribudubois.net> From: Peter Maydell Date: Sat, 6 Feb 2016 20:20:19 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 4/6] i.MX: Add i.MX6 System Reset Controller device. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jean-Christophe DUBOIS Cc: QEMU Developers , Peter Crosthwaite On 6 February 2016 at 20:07, Jean-Christophe DUBOIS w= rote: > Le 02/02/2016 17:46, Peter Maydell a =C3=A9crit : >> >> On 26 January 2016 at 21:45, Jean-Christophe Dubois >> wrote: >>> +static void imx6_src_reset(DeviceState *dev) >>> +{ >>> + IMX6SRCState *s =3D IMX6_SRC(dev); >>> + >>> + DPRINTF("\n"); >>> + >>> + /* >>> + * We only clear the first registers as all GPR registers are >>> preserved >>> + * over resets >>> + */ >>> + memset(s->regs, 0, SRC_GPR1 * sizeof(uint32_t)); >> >> Reset for a QEMU device means "full power cycle reset", so we should >> return the state to the same as if QEMU had just been started. > > > Is there any way to support the warm reset then? If it's purely local to a device (triggered by a register write), just write a function that does what it needs to do. If you need a more machine-wide idea of "warm reset" then things get harder. >> This all looks pretty dangerous to me. Handling power-on of >> another CPU needs careful thought, especially since we're moving >> towards multi-threaded TCG, in which case the other CPU might >> in thory be really running. > > > In i.MX6 (and SOC using the SRC in general) all cores (except core 0 > obviously) are initialized in "powered-off" mode. Therefore they should n= ot > be running before this function is called. > > Basically this code is just an adaptation of a similar code in > target-arm/psci.c. Yeah, I realised that a bit after posting my earlier email. We should factor out the code that's doing the actual work of powering up a different CPU, because then if it does need modification for multi-threading we only have one place to fix. thanks -- PMM