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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , QEMU Developers , CS20 KFTing , qemu-arm , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , IS20 Avi Fishman Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 9 Oct 2020 at 00:22, Havard Skinnemoen wrote: > > The NPCM7xx chips have multiple GPIO controllers that are mostly > identical except for some minor differences like the reset values of > some registers. Each controller controls up to 32 pins. > > Each individual pin is modeled as a pair of unnamed GPIOs -- one for > emitting the actual pin state, and one for driving the pin externally. > Like the nRF51 GPIO controller, a gpio level may be negative, which > means the pin is not driven, or floating. > > Reviewed-by: Tyrone Ting > Signed-off-by: Havard Skinnemoen > +static void npcm7xx_gpio_class_init(ObjectClass *klass, void *data) > +{ > + ResettableClass *reset = RESETTABLE_CLASS(klass); > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + QEMU_BUILD_BUG_ON(NPCM7XX_GPIO_REGS_END > NPCM7XX_GPIO_NR_REGS); > + > + dc->desc = "NPCM7xx GPIO Controller"; > + reset->phases.enter = npcm7xx_gpio_enter_reset; > + reset->phases.hold = npcm7xx_gpio_hold_reset; > + device_class_set_props(dc, npcm7xx_gpio_properties); > +} Missing vmstate struct. Otherwise device looks good. thanks -- PMM