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* [PATCH  v1 0/2] fix for bug 1859021
@ 2020-01-10 16:16 Alex Bennée
  2020-01-10 16:16 ` [PATCH v1 1/2] target/arm: detect 64 bit overflow caused by high cval + voff Alex Bennée
  2020-01-10 16:16 ` [PATCH v1 2/2] tests/tcg: add a vtimer test for aarch64 Alex Bennée
  0 siblings, 2 replies; 16+ messages in thread
From: Alex Bennée @ 2020-01-10 16:16 UTC (permalink / raw)
  To: qemu-devel; +Cc: qemu-arm, Alex Bennée

Hi,

This is a fairly trivial fix for a uint64_t overflow however I spent
some time making sure I understood why we got stuck in a busy loop and
adding tests to both tcg and kvm-unit-tests.

Alex Bennée (2):
  target/arm: detect 64 bit overflow caused by high cval + voff
  tests/tcg: add a vtimer test for aarch64

 target/arm/helper.c                       |  3 +
 tests/tcg/aarch64/system/vtimer.c         | 80 +++++++++++++++++++++++
 tests/tcg/aarch64/Makefile.softmmu-target |  4 ++
 3 files changed, 87 insertions(+)
 create mode 100644 tests/tcg/aarch64/system/vtimer.c

-- 
2.20.1



^ permalink raw reply	[flat|nested] 16+ messages in thread
* [Bug 1859021] [NEW] qemu-system-aarch64 (tcg): cval + voff overflow not handled, causes qemu to hang
@ 2020-01-09 13:24 Alex Longwall
  2020-01-09 14:44 ` [Bug 1859021] " Alex Bennée
                   ` (3 more replies)
  0 siblings, 4 replies; 16+ messages in thread
From: Alex Longwall @ 2020-01-09 13:24 UTC (permalink / raw)
  To: qemu-devel

Public bug reported:

The Armv8 architecture reference manual states that for any timer set
(e.g. CNTP* and CNTV*), the condition for such timer to generate an
interrupt (if enabled & unmasked) is:

CVAL <= CNT(P/V)CT

Although this is arguably sloppy coding, I have seen code that is
therefore assuming it can set CVAL to a very high value (e.g.
UINT64_MAX) and leave the interrupt enabled in CTL, and never get the
interrupt.

On latest master commit as the time of writing, there is an integer
overflow in target/arm/helper.c gt_recalc_timer affecting the virtual
timer when the interrupt is enabled in CTL:

    /* Next transition is when we hit cval */
    nexttick = gt->cval + offset;

When this overflow happens, I notice that qemu is no longer responsive and that I have to SIGKILL the process:
    - qemu takes nearly all the cpu time of the cores it is running on (e.g. 50% cpu usage if running on half the cores) and is completely unresponsive
    - no guest interrupt (reported via -d int) is generated

Here the minimal code example to reproduce the issue:

    mov     x0, #1
    msr     cntvoff_el2, x0
    mov     x0, #-1
    msr     cntv_cval_el0, x0
    mov     x0, #1
    msr     cntv_ctl_el0, x0 // interrupt generation enabled, not masked; qemu will start to hang here

Options used:
-nographic -machine virt,virtualization=on,gic-version=2,accel=tcg -cpu cortex-a57
-smp 4 -m 1024 -kernel whatever.elf -d unimp,guest_errors,int -semihosting-config enable,target=native
-serial mon:stdio

Version used: 4.2

** Affects: qemu
     Importance: Undecided
         Status: New

-- 
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https://bugs.launchpad.net/bugs/1859021

Title:
  qemu-system-aarch64 (tcg):  cval + voff overflow not handled, causes
  qemu to hang

Status in QEMU:
  New

Bug description:
  The Armv8 architecture reference manual states that for any timer set
  (e.g. CNTP* and CNTV*), the condition for such timer to generate an
  interrupt (if enabled & unmasked) is:

  CVAL <= CNT(P/V)CT

  Although this is arguably sloppy coding, I have seen code that is
  therefore assuming it can set CVAL to a very high value (e.g.
  UINT64_MAX) and leave the interrupt enabled in CTL, and never get the
  interrupt.

  On latest master commit as the time of writing, there is an integer
  overflow in target/arm/helper.c gt_recalc_timer affecting the virtual
  timer when the interrupt is enabled in CTL:

      /* Next transition is when we hit cval */
      nexttick = gt->cval + offset;

  When this overflow happens, I notice that qemu is no longer responsive and that I have to SIGKILL the process:
      - qemu takes nearly all the cpu time of the cores it is running on (e.g. 50% cpu usage if running on half the cores) and is completely unresponsive
      - no guest interrupt (reported via -d int) is generated

  Here the minimal code example to reproduce the issue:

      mov     x0, #1
      msr     cntvoff_el2, x0
      mov     x0, #-1
      msr     cntv_cval_el0, x0
      mov     x0, #1
      msr     cntv_ctl_el0, x0 // interrupt generation enabled, not masked; qemu will start to hang here

  Options used:
  -nographic -machine virt,virtualization=on,gic-version=2,accel=tcg -cpu cortex-a57
  -smp 4 -m 1024 -kernel whatever.elf -d unimp,guest_errors,int -semihosting-config enable,target=native
  -serial mon:stdio

  Version used: 4.2

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1859021/+subscriptions


^ permalink raw reply	[flat|nested] 16+ messages in thread

end of thread, other threads:[~2021-05-01  5:42 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-10 16:16 [PATCH v1 0/2] fix for bug 1859021 Alex Bennée
2020-01-10 16:16 ` [PATCH v1 1/2] target/arm: detect 64 bit overflow caused by high cval + voff Alex Bennée
2020-01-10 16:16   ` [Bug 1859021] " Alex Bennée
2020-01-16 18:45   ` Peter Maydell
2020-01-16 18:45     ` [Bug 1859021] " Peter Maydell
2020-01-17 11:50     ` Peter Maydell
2020-01-17 11:50       ` [Bug 1859021] " Peter Maydell
2020-01-10 16:16 ` [PATCH v1 2/2] tests/tcg: add a vtimer test for aarch64 Alex Bennée
2020-01-17 14:07   ` Peter Maydell
2020-02-06 17:00     ` Alex Bennée
  -- strict thread matches above, loose matches on Subject: below --
2020-01-09 13:24 [Bug 1859021] [NEW] qemu-system-aarch64 (tcg): cval + voff overflow not handled, causes qemu to hang Alex Longwall
2020-01-09 14:44 ` [Bug 1859021] " Alex Bennée
2020-01-09 16:25 ` [RFC PATCH] tests/tcg: add a vtimer test for aarch64 Alex Bennée
2020-01-09 16:25   ` [Bug 1859021] Re: qemu-system-aarch64 (tcg): cval + voff overflow not handled, causes qemu to hang Alex Bennée
2020-07-28 14:44 ` Alex Bennée
2021-05-01  5:30 ` Thomas Huth

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