From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH v5 14/22] target/arm: Implement the access tag cache flushes
Date: Thu, 5 Dec 2019 17:49:26 +0000 [thread overview]
Message-ID: <CAFEAcA9tHvwN-FbVWoMRfidGC8uJD6k8w=ucs537Gh-=CtmxeA@mail.gmail.com> (raw)
In-Reply-To: <20191011134744.2477-15-richard.henderson@linaro.org>
On Fri, 11 Oct 2019 at 14:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Like the regular data cache flushes, these are nops within qemu.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/helper.c | 48 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index f435a8d8bd..33bc176e1c 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -5978,6 +5978,54 @@ static const ARMCPRegInfo mte_reginfo[] = {
> { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
> .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
> + { .name = "IGVAC", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "IGSW", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "IGDVAC", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "IGDSW", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "CGSW", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "CGDSW", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "CIGSW", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "CIGDSW", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "CGVAC", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "CGDVAC", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "CGVAP", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "CGDVAP", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "CGVADP", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "CGDVADP", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "CIGVAC", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
> + .type = ARM_CP_NOP, .access = PL1_W },
> + { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
> + .type = ARM_CP_NOP, .access = PL1_W },
> REGINFO_SENTINEL
> };
Some of these, but not all, are conditionally available at EL0,
which means that for those that are:
* .access should be PL0_W
* .accessfn should be aa64_cacheop_access() (which checks
SCTLR_EL1.UCI)
* they need to be in a reginfo that makes them available
for the insns-and-regs-only flavour of MTE
thanks
-- PMM
next prev parent reply other threads:[~2019-12-05 18:02 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-11 13:47 [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, system mode Richard Henderson
2019-10-11 13:47 ` [PATCH v5 01/22] target/arm: Add MTE_ACTIVE to tb_flags Richard Henderson
2019-10-11 13:47 ` [PATCH v5 02/22] target/arm: Add regime_has_2_ranges Richard Henderson
2019-12-03 11:01 ` Peter Maydell
2019-12-03 15:09 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 03/22] target/arm: Add MTE system registers Richard Henderson
2019-12-03 11:48 ` Peter Maydell
2019-12-06 14:47 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 04/22] target/arm: Add helper_mte_check{1,2,3} Richard Henderson
2019-12-03 13:42 ` Peter Maydell
2019-12-03 16:06 ` Richard Henderson
2019-12-03 16:26 ` Peter Maydell
2019-12-03 16:14 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 05/22] target/arm: Suppress tag check for sp+offset Richard Henderson
2019-12-03 14:07 ` Peter Maydell
2020-02-17 21:32 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 06/22] target/arm: Implement the IRG instruction Richard Henderson
2019-12-03 14:26 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 07/22] target/arm: Implement ADDG, SUBG instructions Richard Henderson
2019-10-11 13:47 ` [PATCH v5 08/22] target/arm: Implement the GMI instruction Richard Henderson
2019-10-11 13:47 ` [PATCH v5 09/22] target/arm: Implement the SUBP instruction Richard Henderson
2019-10-11 13:47 ` [PATCH v5 10/22] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY Richard Henderson
2019-12-05 16:12 ` Peter Maydell
2020-02-17 22:56 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 11/22] target/arm: Implement LDG, STG, ST2G instructions Richard Henderson
2019-12-05 17:07 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 12/22] target/arm: Implement the STGP instruction Richard Henderson
2019-12-05 17:15 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 13/22] target/arm: Implement the LDGM and STGM instructions Richard Henderson
2019-12-05 17:42 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 14/22] target/arm: Implement the access tag cache flushes Richard Henderson
2019-12-05 17:49 ` Peter Maydell [this message]
2019-10-11 13:47 ` [PATCH v5 15/22] target/arm: Clean address for DC ZVA Richard Henderson
2019-12-05 17:54 ` Peter Maydell
2019-12-05 18:58 ` Peter Maydell
2020-02-18 0:50 ` Richard Henderson
2020-02-18 11:10 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 16/22] target/arm: Implement data cache set allocation tags Richard Henderson
2019-12-05 18:17 ` Peter Maydell
2020-02-18 1:19 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 17/22] target/arm: Set PSTATE.TCO on exception entry Richard Henderson
2019-10-11 13:47 ` [PATCH v5 18/22] target/arm: Enable MTE Richard Henderson
2019-12-05 18:23 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 19/22] target/arm: Cache the Tagged bit for a page in MemTxAttrs Richard Henderson
2019-12-05 18:32 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 20/22] target/arm: Create tagged ram when MTE is enabled Richard Henderson
2019-12-05 18:40 ` Peter Maydell
2019-12-05 19:24 ` Richard Henderson
2019-12-06 9:51 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 21/22] target/arm: Add mmu indexes for tag memory Richard Henderson
2019-12-06 11:46 ` Peter Maydell
2019-12-06 14:03 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 22/22] target/arm: Add allocation tag storage for system mode Richard Henderson
2019-12-06 13:02 ` Peter Maydell
2019-12-06 14:14 ` Richard Henderson
2019-10-11 19:32 ` [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, " no-reply
2019-10-15 20:39 ` Evgenii Stepanov
2019-10-15 22:04 ` Richard Henderson
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