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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers , Stephen Long Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, 3 Jun 2020 at 02:13, Richard Henderson wrote: > > Fill out the stub that was added earlier. > > Signed-off-by: Richard Henderson > --- > target/arm/internals.h | 47 +++++++++++++++ > target/arm/mte_helper.c | 126 +++++++++++++++++++++++++++++++++++++++- > 2 files changed, 172 insertions(+), 1 deletion(-) > +/* > + * For TBI, ideally, we would do nothing. Proper behaviour on fault is > + * for the tag to be present in the FAR_ELx register. But for user-only > + * mode, we do not have a TLB with which to implement this, so we must > + * remote the top byte. "remove" > + */ > +static inline uint64_t useronly_clean_ptr(uint64_t ptr) > +{ > + /* TBI is known to be enabled. */ > +#ifdef CONFIG_USER_ONLY > + ptr = sextract64(ptr, 0, 56); > +#endif > + return ptr; > +} > + > +/* No-fault version of mte_check1, to be used by SVE for MemSingleNF. */ > +bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra) If this is a no-fault version, why do we need to pass in the ra ? > +{ > + int bit55 = extract64(ptr, 55, 1); > + > + /* If TBI is disabled, the access is unchecked. */ > + if (unlikely(!tbi_check(desc, bit55))) { > + return true; > + } > + > + return mte_probe1_int(env, desc, ptr, ra, bit55); > +} thanks -- PMM