From: Peter Maydell <peter.maydell@linaro.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: QEMU Trivial <qemu-trivial@nongnu.org>,
Alistair Francis <alistair@alistair23.me>,
QEMU Developers <qemu-devel@nongnu.org>,
qemu-arm <qemu-arm@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
Seth Kintigh <skintigh@gmail.com>
Subject: Re: [PATCH v3] hw/adc/stm32f2xx_adc: Correct memory region size and access size
Date: Fri, 5 Jun 2020 14:29:24 +0100 [thread overview]
Message-ID: <CAFEAcA_SZ=Byk8_-GURDEWP+WuaJXwYF9rz1b+4XwPi8GSf9wA@mail.gmail.com> (raw)
In-Reply-To: <20200603055915.17678-1-f4bug@amsat.org>
On Wed, 3 Jun 2020 at 06:59, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> The ADC region size is 256B, split as:
> - [0x00 - 0x4f] defined
> - [0x50 - 0xff] reserved
>
> All registers are 32-bit (thus when the datasheet mentions the
> last defined register is 0x4c, it means its address range is
> 0x4c .. 0x4f.
>
> This model implementation is also 32-bit. Set MemoryRegionOps
> 'impl' fields.
>
> See:
> 'RM0033 Reference manual Rev 8', Table 10.13.18 "ADC register map".
>
> Reported-by: Seth Kintigh <skintigh@gmail.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Applied to target-arm.next, thanks.
-- PMM
prev parent reply other threads:[~2020-06-05 13:30 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-03 5:59 [PATCH v3] hw/adc/stm32f2xx_adc: Correct memory region size and access size Philippe Mathieu-Daudé
2020-06-05 13:29 ` Peter Maydell [this message]
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