From: Peter Maydell <peter.maydell@linaro.org>
To: Alexander Graf <agraf@csgraf.de>
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
qemu-arm@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-devel@nongnu.org,
"Andrei Warkentin" <andrey.warkentin@gmail.com>
Subject: Re: [PATCH] arm: Don't remove EL3 exposure for SMC conduit
Date: Mon, 15 Nov 2021 10:46:30 +0000 [thread overview]
Message-ID: <CAFEAcA_SzCtyDJfnJLLT57Xuf-TdJHRLEW00E7tQkdresxokMg@mail.gmail.com> (raw)
In-Reply-To: <8639608F-1685-48B8-B965-255D30B213F8@csgraf.de>
On Sun, 14 Nov 2021 at 17:41, Alexander Graf <agraf@csgraf.de> wrote:
>
>
>
> > Am 14.11.2021 um 18:20 schrieb Peter Maydell <peter.maydell@linaro.org>:
> > This is tricky, because we use the cpu->isar values to determine whether
> > we should be emulating things. So this change means we now create an
> > inconsistent CPU which in some ways claims to have EL3 (the ISAR ID
> > bits say so) and in some ways does not (the ARM_FEATURE_EL3 flag is
> > unset), and depending on which of the two "do we have EL3?" methods
> > any bit of the TCG code is using will give different results...
>
> Do you think it would be sufficient to go through all readers of the isar bits and guard them behind an ARM_FEATURE_EL3 check in addition? I'll be happy to do so then! :)
That would be a big reverse-course on a design choice we made that
the preference is to look at the ID registers and phase out the
use of ARM_FEATURE bits where possible.
-- PMM
next prev parent reply other threads:[~2021-11-15 10:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-14 10:56 [PATCH] arm: Don't remove EL3 exposure for SMC conduit Alexander Graf
2021-11-14 17:20 ` Peter Maydell
2021-11-14 17:41 ` Alexander Graf
2021-11-14 21:35 ` Alexander Graf
2021-11-15 10:46 ` Peter Maydell [this message]
2021-11-15 11:38 ` Alexander Graf
2021-11-15 12:08 ` Alex Bennée
2021-11-15 12:54 ` Alexander Graf
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