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From: Peter Maydell <peter.maydell@linaro.org>
Date: Tue, 9 Feb 2016 17:37:56 +0000
Message-ID: <CAFEAcA_c=5sz0nVJg3ho6BVNwMqVovMTRghMXOSjATCBBVC-Rg@mail.gmail.com>
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Subject: Re: [Qemu-devel] [PATCH v2 4/5] target-arm: Add PMUSERENR_EL0
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To: Alistair Francis <alistair.francis@xilinx.com>
Cc: Christopher Covington <cov@codeaurora.org>, Peter Crosthwaite <crosthwaitepeter@gmail.com>, QEMU Developers <qemu-devel@nongnu.org>, Aaron Lindsay <alindsay@codeaurora.org>, Nathan Rossi <nathan@nathanrossi.com>

On 6 February 2016 at 00:55, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> The Linux kernel accesses this register early in its setup.
>
> Signed-off-by: Christopher Covington <christopher.covington@linaro.org>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
>
>  target-arm/helper.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 8d401c6..b4bf6fa 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1094,6 +1094,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
>        .resetvalue = 0,
>        .writefn = pmuserenr_write, .raw_writefn = raw_write },
> +    { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
> +      .access = PL0_R | PL1_RW,
> +      .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
> +      .resetvalue = 0,
> +      .writefn = pmuserenr_write, .raw_writefn = raw_write },

Either this or the 32-bit version need to be marked ARM_CP_ALIAS.

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM