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b=0K618xC1z8x8aDaS7IxB3RbPewhi+8mQuSSpF6AGmJAe0cIncmMDRkulS1LOBIt1GB ECBs2gDhdldMOt8icAT/h2Pj10wHG21Nw4Yh7XfbVoLGqQcGXwzPBXL1llK9p0+vZwfj V5Mo79x96gLo8mNobRxUd7C1AYZvCRKrvOuNUiB0nLFPNN1KL1RxL7YApA1gpmFH0RXt 4u2xxiRZuh0ghpVRWY0GIBwOEnKUzH3+kUNnsuyW/tG98U178WAzry7uf/ahYhWUm514 LBx+fAZDAQYXw1Ku9T2z+2ueS/GyJExfxjt3iijPEvvgxf5iwNaIILHa4Osv+Zp8KUdT tXPw== X-Gm-Message-State: ACrzQf3MT/nfoGi6y0rOBTftiFXv2Z09MFc26KO4cgM2iPuEE0GCGR3H M25FUa6a5TQXSLsaCOKoEEmsA+VUkfnUrMoFMqZaxg== X-Google-Smtp-Source: AMsMyM6u1yQ8WNcU6NYv5kqiUuAZd22EpRqpBF2eh33fjdj5ajRAcXm+Q+xiLki8WjmP/yxFMpZ0Msu1VEhsP3uQ4RE= X-Received: by 2002:a05:6402:35c5:b0:450:4b7d:9c49 with SMTP id z5-20020a05640235c500b004504b7d9c49mr22741440edc.149.1664201685305; Mon, 26 Sep 2022 07:14:45 -0700 (PDT) MIME-Version: 1.0 References: <20220926133904.3297263-1-alex.bennee@linaro.org> <20220926133904.3297263-6-alex.bennee@linaro.org> In-Reply-To: <20220926133904.3297263-6-alex.bennee@linaro.org> From: Peter Maydell Date: Mon, 26 Sep 2022 15:14:34 +0100 Message-ID: Subject: Re: [PATCH v2 05/11] hw/intc/gic: use MxTxAttrs to divine accessing CPU To: =?UTF-8?B?QWxleCBCZW5uw6ll?= Cc: qemu-devel@nongnu.org, f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org, Richard Henderson Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, 26 Sept 2022 at 14:39, Alex Benn=C3=A9e wr= ote: > > Now that MxTxAttrs encodes a CPU we should use that to figure it out. > This solves edge cases like accessing via gdbstub or qtest. > > Reviewed-by: Richard Henderson > Signed-off-by: Alex Benn=C3=A9e > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 > > --- > v2 > - update for new field > - bool asserts > --- > hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- > 1 file changed, 22 insertions(+), 17 deletions(-) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index 492b2421ab..d907df3884 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -56,17 +56,22 @@ static const uint8_t gic_id_gicv2[] =3D { > 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0x= b1 > }; > > -static inline int gic_get_current_cpu(GICState *s) > +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) > { > - if (!qtest_enabled() && s->num_cpu > 1) { > - return current_cpu->cpu_index; > - } > - return 0; > + /* > + * Something other than a CPU accessing the GIC would be a bug as > + * would a CPU index higher than the GICState expects to be > + * handling > + */ > + g_assert(attrs.requester_type =3D=3D MEMTXATTRS_CPU); > + g_assert(attrs.requester_id < s->num_cpu); Would it be a QEMU bug, or a guest code bug ? If it's possible for the guest to mis-program a DMA controller to do a read that goes through this function, we shouldn't assert. (Whether that can happen will depend on how the board/SoC code puts together the MemoryRegion hierarchy, I think.) thanks -- PMM