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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Huacai Chen , Aleksandar Rikalo , Eduardo Habkost , Paul Burton , "Edgar E . Iglesias" , "qemu-devel@nongnu.org" , Wainer dos Santos Moschetta , =?UTF-8?Q?Herv=C3=A9_Poussineau?= , Jiaxun Yang , Cleber Rosa , Huacai Chen , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000a5445405b08bbbbf Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Monday, September 28, 2020, Philippe Mathieu-Daud=C3=A9 wrote: > The get_random() helper uses the CP0_Wired register, which is > unrelated to the CP0_Count register use as timer. > Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file") > incorrectly moved this get_random() helper with timer specific > code. Move it back to generic CP0 helpers. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- Reviewed-by: Aleksandar Markovic > target/mips/internal.h | 2 +- > target/mips/cp0_helper.c | 25 +++++++++++++++++++++++++ > target/mips/cp0_timer.c | 25 ------------------------- > 3 files changed, 26 insertions(+), 26 deletions(-) > > diff --git a/target/mips/internal.h b/target/mips/internal.h > index 7f159a9230c..087cabaa6d4 100644 > --- a/target/mips/internal.h > +++ b/target/mips/internal.h > @@ -144,6 +144,7 @@ void r4k_helper_tlbr(CPUMIPSState *env); > void r4k_helper_tlbinv(CPUMIPSState *env); > void r4k_helper_tlbinvf(CPUMIPSState *env); > void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); > +uint32_t cpu_mips_get_random(CPUMIPSState *env); > > void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, > vaddr addr, unsigned size, > @@ -209,7 +210,6 @@ void cpu_state_reset(CPUMIPSState *s); > void cpu_mips_realize_env(CPUMIPSState *env); > > /* cp0_timer.c */ > -uint32_t cpu_mips_get_random(CPUMIPSState *env); > uint32_t cpu_mips_get_count(CPUMIPSState *env); > void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); > void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); > diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c > index de64add038b..12143ac55b9 100644 > --- a/target/mips/cp0_helper.c > +++ b/target/mips/cp0_helper.c > @@ -203,6 +203,31 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int t= c) > *tcst |=3D asid; > } > > +/* XXX: do not use a global */ > +uint32_t cpu_mips_get_random(CPUMIPSState *env) > +{ > + static uint32_t seed =3D 1; > + static uint32_t prev_idx; > + uint32_t idx; > + uint32_t nb_rand_tlb =3D env->tlb->nb_tlb - env->CP0_Wired; > + > + if (nb_rand_tlb =3D=3D 1) { > + return env->tlb->nb_tlb - 1; > + } > + > + /* Don't return same value twice, so get another value */ > + do { > + /* > + * Use a simple algorithm of Linear Congruential Generator > + * from ISO/IEC 9899 standard. > + */ > + seed =3D 1103515245 * seed + 12345; > + idx =3D (seed >> 16) % nb_rand_tlb + env->CP0_Wired; > + } while (idx =3D=3D prev_idx); > + prev_idx =3D idx; > + return idx; > +} > + > /* CP0 helpers */ > target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) > { > diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c > index bd7efb152dd..9c38e9da1c8 100644 > --- a/target/mips/cp0_timer.c > +++ b/target/mips/cp0_timer.c > @@ -29,31 +29,6 @@ > > #define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */ > > -/* XXX: do not use a global */ > -uint32_t cpu_mips_get_random(CPUMIPSState *env) > -{ > - static uint32_t seed =3D 1; > - static uint32_t prev_idx =3D 0; > - uint32_t idx; > - uint32_t nb_rand_tlb =3D env->tlb->nb_tlb - env->CP0_Wired; > - > - if (nb_rand_tlb =3D=3D 1) { > - return env->tlb->nb_tlb - 1; > - } > - > - /* Don't return same value twice, so get another value */ > - do { > - /* > - * Use a simple algorithm of Linear Congruential Generator > - * from ISO/IEC 9899 standard. > - */ > - seed =3D 1103515245 * seed + 12345; > - idx =3D (seed >> 16) % nb_rand_tlb + env->CP0_Wired; > - } while (idx =3D=3D prev_idx); > - prev_idx =3D idx; > - return idx; > -} > - > /* MIPS R4K timer */ > static void cpu_mips_timer_update(CPUMIPSState *env) > { > -- > 2.26.2 > > --000000000000a5445405b08bbbbf Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Monday, September 28, 2020, Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org> wrote:
The get_random() helper uses the CP0_Wired register, w= hich is
unrelated to the CP0_Count register use as timer.
Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file")=
incorrectly moved this get_random() helper with timer specific
code. Move it back to generic CP0 helpers.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---

Reviewed-by: Aleksandar Markovic= <aleksandar.qe= mu.devel@gmail.com>
=C2=A0
=C2=A0target/mips/internal.h=C2=A0 =C2=A0|=C2=A0 2 +-
=C2=A0target/mips/cp0_helper.c | 25 +++++++++++++++++++++++++
=C2=A0target/mips/cp0_timer.c=C2=A0 | 25 -------------------------
=C2=A03 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 7f159a9230c..087cabaa6d4 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -144,6 +144,7 @@ void r4k_helper_tlbr(CPUMIPSState *env);
=C2=A0void r4k_helper_tlbinv(CPUMIPSState *env);
=C2=A0void r4k_helper_tlbinvf(CPUMIPSState *env);
=C2=A0void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extr= a);
+uint32_t cpu_mips_get_random(CPUMIPSState *env);

=C2=A0void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physadd= r,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0vaddr addr, unsi= gned size,
@@ -209,7 +210,6 @@ void cpu_state_reset(CPUMIPSState *s);
=C2=A0void cpu_mips_realize_env(CPUMIPSState *env);

=C2=A0/* cp0_timer.c */
-uint32_t cpu_mips_get_random(CPUMIPSState *env);
=C2=A0uint32_t cpu_mips_get_count(CPUMIPSState *env);
=C2=A0void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); =C2=A0void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);<= br> diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index de64add038b..12143ac55b9 100644
--- a/target/mips/cp0_helper.c
+++ b/target/mips/cp0_helper.c
@@ -203,6 +203,31 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)=
=C2=A0 =C2=A0 =C2=A0*tcst |=3D asid;
=C2=A0}

+/* XXX: do not use a global */
+uint32_t cpu_mips_get_random(CPUMIPSState *env)
+{
+=C2=A0 =C2=A0 static uint32_t seed =3D 1;
+=C2=A0 =C2=A0 static uint32_t prev_idx;
+=C2=A0 =C2=A0 uint32_t idx;
+=C2=A0 =C2=A0 uint32_t nb_rand_tlb =3D env->tlb->nb_tlb - env->CP= 0_Wired;
+
+=C2=A0 =C2=A0 if (nb_rand_tlb =3D=3D 1) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return env->tlb->nb_tlb - 1;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /* Don't return same value twice, so get another value *= /
+=C2=A0 =C2=A0 do {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* Use a simple algorithm of Linear Congr= uential Generator
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* from ISO/IEC 9899 standard.
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 seed =3D 1103515245 * seed + 12345;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 idx =3D (seed >> 16) % nb_rand_tlb + env= ->CP0_Wired;
+=C2=A0 =C2=A0 } while (idx =3D=3D prev_idx);
+=C2=A0 =C2=A0 prev_idx =3D idx;
+=C2=A0 =C2=A0 return idx;
+}
+
=C2=A0/* CP0 helpers */
=C2=A0target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
=C2=A0{
diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c
index bd7efb152dd..9c38e9da1c8 100644
--- a/target/mips/cp0_timer.c
+++ b/target/mips/cp0_timer.c
@@ -29,31 +29,6 @@

=C2=A0#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */

-/* XXX: do not use a global */
-uint32_t cpu_mips_get_random(CPUMIPSState *env)
-{
-=C2=A0 =C2=A0 static uint32_t seed =3D 1;
-=C2=A0 =C2=A0 static uint32_t prev_idx =3D 0;
-=C2=A0 =C2=A0 uint32_t idx;
-=C2=A0 =C2=A0 uint32_t nb_rand_tlb =3D env->tlb->nb_tlb - env->CP= 0_Wired;
-
-=C2=A0 =C2=A0 if (nb_rand_tlb =3D=3D 1) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 return env->tlb->nb_tlb - 1;
-=C2=A0 =C2=A0 }
-
-=C2=A0 =C2=A0 /* Don't return same value twice, so get another value *= /
-=C2=A0 =C2=A0 do {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* Use a simple algorithm of Linear Congr= uential Generator
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* from ISO/IEC 9899 standard.
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 seed =3D 1103515245 * seed + 12345;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 idx =3D (seed >> 16) % nb_rand_tlb + env= ->CP0_Wired;
-=C2=A0 =C2=A0 } while (idx =3D=3D prev_idx);
-=C2=A0 =C2=A0 prev_idx =3D idx;
-=C2=A0 =C2=A0 return idx;
-}
-
=C2=A0/* MIPS R4K timer */
=C2=A0static void cpu_mips_timer_update(CPUMIPSState *env)
=C2=A0{
--
2.26.2

--000000000000a5445405b08bbbbf--