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Fri, 15 Jan 2021 13:49:43 -0800 (PST) MIME-Version: 1.0 References: <1610427124-49887-1-git-send-email-bmeng.cn@gmail.com> <1610427124-49887-2-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1610427124-49887-2-git-send-email-bmeng.cn@gmail.com> From: Alistair Francis Date: Fri, 15 Jan 2021 13:49:17 -0800 Message-ID: Subject: Re: [PATCH 1/4] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external To: Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::d35; envelope-from=alistair23@gmail.com; helo=mail-io1-xd35.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Bin Meng , Alistair Francis , "qemu-devel@nongnu.org Developers" , Jim Wilson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Jan 11, 2021 at 8:53 PM Bin Meng wrote: > > From: Bin Meng > > In preparation to generate the CSR register list for GDB stub > dynamically, change csr_ops[] to non-static so that it can be > referenced externally. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > target/riscv/cpu.h | 8 ++++++++ > target/riscv/csr.c | 10 +--------- > 2 files changed, 9 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 2649949..6f9e1cc 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -482,6 +482,14 @@ typedef struct { > riscv_csr_op_fn op; > } riscv_csr_operations; > > +/* CSR function table constants */ > +enum { > + CSR_TABLE_SIZE = 0x1000 > +}; > + > +/* CSR function table */ > +extern riscv_csr_operations csr_ops[]; > + > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 10ab82e..507e8ee 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -23,14 +23,6 @@ > #include "qemu/main-loop.h" > #include "exec/exec-all.h" > > -/* CSR function table */ > -static riscv_csr_operations csr_ops[]; > - > -/* CSR function table constants */ > -enum { > - CSR_TABLE_SIZE = 0x1000 > -}; > - > /* CSR function table public API */ > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) > { > @@ -1378,7 +1370,7 @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, > } > > /* Control and Status Register function table */ > -static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > +riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > /* User Floating-Point CSRs */ > [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, > [CSR_FRM] = { fs, read_frm, write_frm }, > -- > 2.7.4 > >