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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::12f; envelope-from=alistair23@gmail.com; helo=mail-il1-x12f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Bin Meng , Richard Henderson , "qemu-devel@nongnu.org Developers" , Palmer Dabbelt , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Oct 15, 2021 at 6:25 PM wrote: > > From: Frank Chang > > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn32.decode | 2 +- > target/riscv/insn_trans/trans_rvv.c.inc | 10 ++++++++-- > 2 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index d139c0aade7..3ac5162aeb7 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -632,7 +632,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm > vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm > vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm > vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm > -viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm > +viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm > vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm > vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r > vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 538a32a605a..3751496676f 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -2756,12 +2756,18 @@ GEN_M_TRANS(vmsbf_m) > GEN_M_TRANS(vmsif_m) > GEN_M_TRANS(vmsof_m) > > -/* Vector Iota Instruction */ > +/* > + * Vector Iota Instruction > + * > + * 1. The destination register cannot overlap the source register. > + * 2. If masked, cannot overlap the mask register ('v0'). > + * 3. An illegal instruction exception is raised if vstart is non-zero. > + */ > static bool trans_viota_m(DisasContext *s, arg_viota_m *a) > { > if (require_rvv(s) && > vext_check_isa_ill(s) && > - require_noover(a->rd, s->lmul, a->rs2, 0) && > + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && > require_vm(a->vm, a->rd) && > require_align(a->rd, s->lmul)) { > uint32_t data = 0; > -- > 2.25.1 > >