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From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: guoren@linux.alibaba.com,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	wxy194768@alibaba-inc.com,
	Chih-Min Chao <chihmin.chao@sifive.com>,
	wenmeng_zhang@c-sky.com, Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v6 20/61] target/riscv: vector widening integer multiply instructions
Date: Wed, 25 Mar 2020 10:25:20 -0700
Message-ID: <CAKmqyKMCtP=rKYgser0V5me6mFgyaFqf1jAHrU0MrF2-1X4Gdg@mail.gmail.com> (raw)
In-Reply-To: <20200317150653.9008-21-zhiwei_liu@c-sky.com>

On Tue, Mar 17, 2020 at 8:47 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/helper.h                   | 19 +++++++++
>  target/riscv/insn32.decode              |  6 +++
>  target/riscv/insn_trans/trans_rvv.inc.c |  8 ++++
>  target/riscv/vector_helper.c            | 51 +++++++++++++++++++++++++
>  4 files changed, 84 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 357f149198..1704b8c512 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -591,3 +591,22 @@ DEF_HELPER_6(vrem_vx_b, void, ptr, ptr, tl, ptr, env, i32)
>  DEF_HELPER_6(vrem_vx_h, void, ptr, ptr, tl, ptr, env, i32)
>  DEF_HELPER_6(vrem_vx_w, void, ptr, ptr, tl, ptr, env, i32)
>  DEF_HELPER_6(vrem_vx_d, void, ptr, ptr, tl, ptr, env, i32)
> +
> +DEF_HELPER_6(vwmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vwmulu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vwmulu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vwmulu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vwmulsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vwmulsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vwmulsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vwmul_vx_b, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vwmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vwmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vwmulu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vwmulu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vwmulu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vwmulsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vwmulsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vwmulsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 7fb8f8fad8..ae7cfa3e28 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -379,6 +379,12 @@ vremu_vv        100010 . ..... ..... 010 ..... 1010111 @r_vm
>  vremu_vx        100010 . ..... ..... 110 ..... 1010111 @r_vm
>  vrem_vv         100011 . ..... ..... 010 ..... 1010111 @r_vm
>  vrem_vx         100011 . ..... ..... 110 ..... 1010111 @r_vm
> +vwmulu_vv       111000 . ..... ..... 010 ..... 1010111 @r_vm
> +vwmulu_vx       111000 . ..... ..... 110 ..... 1010111 @r_vm
> +vwmulsu_vv      111010 . ..... ..... 010 ..... 1010111 @r_vm
> +vwmulsu_vx      111010 . ..... ..... 110 ..... 1010111 @r_vm
> +vwmul_vv        111011 . ..... ..... 010 ..... 1010111 @r_vm
> +vwmul_vx        111011 . ..... ..... 110 ..... 1010111 @r_vm
>
>  vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
>  vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
> index ed53eaaef5..98df7e2daa 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -1472,3 +1472,11 @@ GEN_OPIVX_TRANS(vdivu_vx, opivx_check)
>  GEN_OPIVX_TRANS(vdiv_vx, opivx_check)
>  GEN_OPIVX_TRANS(vremu_vx, opivx_check)
>  GEN_OPIVX_TRANS(vrem_vx, opivx_check)
> +
> +/* Vector Widening Integer Multiply Instructions */
> +GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check)
> +GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check)
> +GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check)
> +GEN_OPIVX_WIDEN_TRANS(vwmul_vx)
> +GEN_OPIVX_WIDEN_TRANS(vwmulu_vx)
> +GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx)
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 4fc7a08954..35c6aa8494 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -856,6 +856,18 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl)
>  #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
>  #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
>  #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t
> +#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
> +#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
> +#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
> +#define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
> +#define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
> +#define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
> +#define WOP_SUS_B int16_t, uint8_t, int8_t, uint16_t, int16_t
> +#define WOP_SUS_H int32_t, uint16_t, int16_t, uint32_t, int32_t
> +#define WOP_SUS_W int64_t, uint32_t, int32_t, uint64_t, int64_t
> +#define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t
> +#define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t
> +#define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t
>
>  /* operation of two vector elements */
>  typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
> @@ -1815,3 +1827,42 @@ GEN_VEXT_VX(vrem_vx_b, 1, 1, clearb)
>  GEN_VEXT_VX(vrem_vx_h, 2, 2, clearh)
>  GEN_VEXT_VX(vrem_vx_w, 4, 4, clearl)
>  GEN_VEXT_VX(vrem_vx_d, 8, 8, clearq)
> +
> +/* Vector Widening Integer Multiply Instructions */
> +RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL)
> +RVVCALL(OPIVV2, vwmul_vv_h, WOP_SSS_H, H4, H2, H2, DO_MUL)
> +RVVCALL(OPIVV2, vwmul_vv_w, WOP_SSS_W, H8, H4, H4, DO_MUL)
> +RVVCALL(OPIVV2, vwmulu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MUL)
> +RVVCALL(OPIVV2, vwmulu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MUL)
> +RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL)
> +RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL)
> +RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL)
> +RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL)
> +GEN_VEXT_VV(vwmul_vv_b, 1, 2, clearh)
> +GEN_VEXT_VV(vwmul_vv_h, 2, 4, clearl)
> +GEN_VEXT_VV(vwmul_vv_w, 4, 8, clearq)
> +GEN_VEXT_VV(vwmulu_vv_b, 1, 2, clearh)
> +GEN_VEXT_VV(vwmulu_vv_h, 2, 4, clearl)
> +GEN_VEXT_VV(vwmulu_vv_w, 4, 8, clearq)
> +GEN_VEXT_VV(vwmulsu_vv_b, 1, 2, clearh)
> +GEN_VEXT_VV(vwmulsu_vv_h, 2, 4, clearl)
> +GEN_VEXT_VV(vwmulsu_vv_w, 4, 8, clearq)
> +
> +RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL)
> +RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL)
> +RVVCALL(OPIVX2, vwmul_vx_w, WOP_SSS_W, H8, H4, DO_MUL)
> +RVVCALL(OPIVX2, vwmulu_vx_b, WOP_UUU_B, H2, H1, DO_MUL)
> +RVVCALL(OPIVX2, vwmulu_vx_h, WOP_UUU_H, H4, H2, DO_MUL)
> +RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL)
> +RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL)
> +RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL)
> +RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL)
> +GEN_VEXT_VX(vwmul_vx_b, 1, 2, clearh)
> +GEN_VEXT_VX(vwmul_vx_h, 2, 4, clearl)
> +GEN_VEXT_VX(vwmul_vx_w, 4, 8, clearq)
> +GEN_VEXT_VX(vwmulu_vx_b, 1, 2, clearh)
> +GEN_VEXT_VX(vwmulu_vx_h, 2, 4, clearl)
> +GEN_VEXT_VX(vwmulu_vx_w, 4, 8, clearq)
> +GEN_VEXT_VX(vwmulsu_vx_b, 1, 2, clearh)
> +GEN_VEXT_VX(vwmulsu_vx_h, 2, 4, clearl)
> +GEN_VEXT_VX(vwmulsu_vx_w, 4, 8, clearq)
> --
> 2.23.0
>


  reply index

Thread overview: 120+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-17 15:05 [PATCH v6 00/61] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-03-17 15:05 ` [PATCH v6 01/61] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-03-17 15:05 ` [PATCH v6 02/61] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-03-17 15:05 ` [PATCH v6 03/61] target/riscv: support vector extension csr LIU Zhiwei
2020-03-17 15:05 ` [PATCH v6 04/61] target/riscv: add vector configure instruction LIU Zhiwei
2020-03-23  6:51   ` Kito Cheng
2020-03-23  7:10     ` LIU Zhiwei
2020-03-17 15:05 ` [PATCH v6 05/61] target/riscv: add an internals.h header LIU Zhiwei
2020-03-18 23:45   ` Alistair Francis
2020-03-27 23:41   ` Richard Henderson
2020-03-17 15:05 ` [PATCH v6 06/61] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-03-18 23:54   ` Alistair Francis
2020-03-17 15:05 ` [PATCH v6 07/61] target/riscv: add vector index " LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 08/61] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 09/61] target/riscv: add vector amo operations LIU Zhiwei
2020-03-19 17:01   ` Alistair Francis
2020-03-27 23:44   ` Richard Henderson
2020-03-17 15:06 ` [PATCH v6 10/61] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-03-20 18:31   ` Alistair Francis
2020-03-27 23:54   ` Richard Henderson
2020-03-28 14:42     ` LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 11/61] target/riscv: vector widening " LIU Zhiwei
2020-03-19 16:28   ` Alistair Francis
2020-03-17 15:06 ` [PATCH v6 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-03-19 17:29   ` Alistair Francis
2020-03-28  0:00   ` Richard Henderson
2020-03-17 15:06 ` [PATCH v6 13/61] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-03-20 18:34   ` Alistair Francis
2020-03-17 15:06 ` [PATCH v6 14/61] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-03-19 20:10   ` Alistair Francis
2020-03-17 15:06 ` [PATCH v6 15/61] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-03-20 18:43   ` Alistair Francis
2020-03-17 15:06 ` [PATCH v6 16/61] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-03-25 17:32   ` Alistair Francis
2020-03-17 15:06 ` [PATCH v6 17/61] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-03-20 18:49   ` Alistair Francis
2020-03-17 15:06 ` [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-03-25 17:36   ` Alistair Francis
2020-03-28  0:06   ` Richard Henderson
2020-03-28 15:17     ` LIU Zhiwei
2020-03-28 15:47       ` Richard Henderson
2020-03-28 16:13         ` LIU Zhiwei
2020-03-29  4:00           ` LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 19/61] target/riscv: vector integer divide instructions LIU Zhiwei
2020-03-20 18:51   ` Alistair Francis
2020-03-17 15:06 ` [PATCH v6 20/61] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-03-25 17:25   ` Alistair Francis [this message]
2020-03-17 15:06 ` [PATCH v6 21/61] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-03-25 17:27   ` Alistair Francis
2020-03-17 15:06 ` [PATCH v6 22/61] target/riscv: vector widening " LIU Zhiwei
2020-03-25 17:42   ` Alistair Francis
2020-03-17 15:06 ` [PATCH v6 23/61] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-03-26 17:57   ` Alistair Francis
2020-03-28  0:18   ` Richard Henderson
2020-03-17 15:06 ` [PATCH v6 24/61] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-03-28  0:20   ` Richard Henderson
2020-03-17 15:06 ` [PATCH v6 25/61] target/riscv: vector single-width averaging " LIU Zhiwei
2020-03-19  3:46   ` LIU Zhiwei
2020-03-28  0:32     ` Richard Henderson
2020-03-28  1:07       ` LIU Zhiwei
2020-03-28  1:22         ` Richard Henderson
2020-03-28 15:37           ` LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-03-28  1:08   ` Richard Henderson
2020-03-28 15:41     ` LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 27/61] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-03-28  1:23   ` Richard Henderson
2020-03-17 15:06 ` [PATCH v6 28/61] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-03-28  1:24   ` Richard Henderson
2020-03-17 15:06 ` [PATCH v6 29/61] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-03-28  1:50   ` Richard Henderson
2020-03-17 15:06 ` [PATCH v6 30/61] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 31/61] target/riscv: vector widening " LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 32/61] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-03-25 17:46   ` Alistair Francis
2020-03-17 15:06 ` [PATCH v6 33/61] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 35/61] target/riscv: vector widening " LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 36/61] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 37/61] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-03-25 17:47   ` Alistair Francis
2020-03-17 15:06 ` [PATCH v6 38/61] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 39/61] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-03-28  2:01   ` Richard Henderson
2020-03-28 15:44     ` LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 40/61] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-03-28  2:06   ` Richard Henderson
2020-03-17 15:06 ` [PATCH v6 41/61] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-03-28  3:23   ` Richard Henderson
2020-03-28 15:47     ` LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 42/61] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 43/61] target/riscv: widening " LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 44/61] target/riscv: narrowing " LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 45/61] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 46/61] target/riscv: vector wideing " LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 47/61] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 48/61] target/riscv: vector widening " LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 49/61] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 50/61] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 51/61] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 52/61] target/riscv: set-X-first " LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 53/61] target/riscv: vector iota instruction LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 54/61] target/riscv: vector element index instruction LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 55/61] target/riscv: integer extract instruction LIU Zhiwei
2020-03-28  3:36   ` Richard Henderson
2020-03-28 16:23     ` LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 56/61] target/riscv: integer scalar move instruction LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 57/61] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-03-28  3:44   ` Richard Henderson
2020-03-28 16:31     ` LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 58/61] target/riscv: vector slide instructions LIU Zhiwei
2020-03-28  3:50   ` Richard Henderson
2020-03-28 13:40   ` LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 59/61] target/riscv: vector register gather instruction LIU Zhiwei
2020-03-28  3:57   ` Richard Henderson
2020-03-17 15:06 ` [PATCH v6 60/61] target/riscv: vector compress instruction LIU Zhiwei
2020-03-17 15:06 ` [PATCH v6 61/61] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-03-25 17:49   ` Alistair Francis
2020-03-28  4:00   ` Richard Henderson
2020-03-17 20:47 ` [PATCH v6 00/61] target/riscv: support vector extension v0.7.1 no-reply

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Archives are clonable:
	git clone --mirror https://lore.kernel.org/qemu-devel/0 qemu-devel/git/0.git
	git clone --mirror https://lore.kernel.org/qemu-devel/1 qemu-devel/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 qemu-devel qemu-devel/ https://lore.kernel.org/qemu-devel \
		qemu-devel@nongnu.org
	public-inbox-index qemu-devel

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.nongnu.qemu-devel


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git