From: Alistair Francis <alistair23@gmail.com>
To: Dylan Jhong <dylan@andestech.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
"Alan Quey-Liang Kao\(\(\(\(\(\(\(\(\(\(\)"
<alankao@andestech.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
x5710999x@gmail.com,
"Ruinland Chuan-Tzu Tsa\(\(\(\(\(\(\(\(\(\(\)"
<ruinland@andestech.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [PATCH V3] target/riscv: Align the data type of reset vector address
Date: Thu, 25 Mar 2021 16:19:09 -0400 [thread overview]
Message-ID: <CAKmqyKMGROe+k8=f=_Vw8eLwo-PF-ENQeoD+WSte_G8dRHmatg@mail.gmail.com> (raw)
In-Reply-To: <20210325094150.28918-1-dylan@andestech.com>
On Thu, Mar 25, 2021 at 5:43 AM Dylan Jhong <dylan@andestech.com> wrote:
>
> Signed-off-by: Dylan Jhong <dylan@andestech.com>
> Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
> ---
> target/riscv/cpu.c | 6 +++++-
> target/riscv/cpu.h | 2 +-
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 7d6ed80f6b..8a5f18bcb0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -137,7 +137,7 @@ static void set_feature(CPURISCVState *env, int feature)
> env->features |= (1ULL << feature);
> }
>
> -static void set_resetvec(CPURISCVState *env, int resetvec)
> +static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
> {
> #ifndef CONFIG_USER_ONLY
> env->resetvec = resetvec;
> @@ -554,7 +554,11 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> +#if defined(TARGET_RISCV32)
> + DEFINE_PROP_UINT32("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
> +#elif defined(TARGET_RISCV64)
> DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
> +#endif
Thanks for the patch!
I don't want to introduce any more define(TARGET_* macros as we are
trying to make RISC-V QEMU xlen independent.
The hexagon port has an example of how you can use target_ulong here:
DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust,
0, qdev_prop_uint32, target_ulong);
can you do something like that instead?
Alistair
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0a33d387ba..d9d7891666 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -303,7 +303,7 @@ struct RISCVCPU {
> uint16_t elen;
> bool mmu;
> bool pmp;
> - uint64_t resetvec;
> + target_ulong resetvec;
> } cfg;
> };
>
> --
> 2.17.1
>
>
next prev parent reply other threads:[~2021-03-25 20:22 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-25 9:41 [PATCH V3] target/riscv: Align the data type of reset vector address Dylan Jhong
2021-03-25 10:20 ` Bin Meng
2021-03-25 20:19 ` Alistair Francis [this message]
2021-03-26 10:18 ` Dylan Jhong
2021-03-26 11:11 ` Peter Maydell
2021-03-28 0:46 ` Alistair Francis
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