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charset="UTF-8" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::d2c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::d2c; envelope-from=alistair23@gmail.com; helo=mail-io1-xd2c.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Bin Meng , Richard Henderson , "qemu-devel@nongnu.org Developers" , Palmer Dabbelt , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Nov 12, 2021 at 2:14 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 2 +- > target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- > target/riscv/vector_helper.c | 8 +++++--- > 3 files changed, 8 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index c5098380dd..f2910f5f30 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -82,7 +82,7 @@ DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl) > #endif > > /* Vector functions */ > -DEF_HELPER_3(vsetvl, tl, env, tl, tl) > +DEF_HELPER_4(vsetvl, tl, env, tl, tl, i32) > DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32) > DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32) > DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32) > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 17ee3babef..6fa673f4b2 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -37,7 +37,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) > } else { > s1 = get_gpr(ctx, a->rs1, EXT_ZERO); > } > - gen_helper_vsetvl(dst, cpu_env, s1, s2); > + gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_i32(get_xlen(ctx))); > gen_set_gpr(ctx, a->rd, dst); > > tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); > @@ -64,7 +64,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a) > } else { > s1 = get_gpr(ctx, a->rs1, EXT_ZERO); > } > - gen_helper_vsetvl(dst, cpu_env, s1, s2); > + gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_i32(get_xlen(ctx))); > gen_set_gpr(ctx, a->rd, dst); > > gen_goto_tb(ctx, 0, ctx->pc_succ_insn); > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index b02ccefa4d..e49b431610 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -27,14 +27,16 @@ > #include > > target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, > - target_ulong s2) > + target_ulong s2, uint32_t xlen) > { > int vlmax, vl; > RISCVCPU *cpu = env_archcpu(env); > uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW); > uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV); > - bool vill = FIELD_EX64(s2, VTYPE, VILL); > - target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED); > + bool vill = (s2 >> (xlen - 1)) & 0x1; > + target_ulong reserved = s2 & > + MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, > + xlen - 1 - R_VTYPE_RESERVED_SHIFT); > > if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) { > /* only set vill bit. */ > -- > 2.25.1 > >