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X-Received-From: 2607:f8b0:4864:20::e43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, "open list:RISC-V" , Richard Henderson , "qemu-devel@nongnu.org Developers" , wxy194768@alibaba-inc.com, Chih-Min Chao , wenmeng_zhang@c-sky.com, Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Mar 17, 2020 at 9:21 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 13 ++++++++++++ > target/riscv/insn32.decode | 4 ++++ > target/riscv/insn_trans/trans_rvv.inc.c | 6 ++++++ > target/riscv/vector_helper.c | 27 +++++++++++++++++++++++++ > 4 files changed, 50 insertions(+) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index a5d3a5a832..47d91933de 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -917,3 +917,16 @@ DEF_HELPER_6(vfwnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32) > DEF_HELPER_5(vfsqrt_v_h, void, ptr, ptr, ptr, env, i32) > DEF_HELPER_5(vfsqrt_v_w, void, ptr, ptr, ptr, env, i32) > DEF_HELPER_5(vfsqrt_v_d, void, ptr, ptr, ptr, env, i32) > + > +DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfmax_vv_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfmax_vv_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfmax_vv_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfmin_vf_h, void, ptr, ptr, i64, ptr, env, i32) > +DEF_HELPER_6(vfmin_vf_w, void, ptr, ptr, i64, ptr, env, i32) > +DEF_HELPER_6(vfmin_vf_d, void, ptr, ptr, i64, ptr, env, i32) > +DEF_HELPER_6(vfmax_vf_h, void, ptr, ptr, i64, ptr, env, i32) > +DEF_HELPER_6(vfmax_vf_w, void, ptr, ptr, i64, ptr, env, i32) > +DEF_HELPER_6(vfmax_vf_d, void, ptr, ptr, i64, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 4ea71eaf39..5ec5595e2c 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -490,6 +490,10 @@ vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm > vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm > vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm > vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm > +vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm > +vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm > +vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm > +vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm > > vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c > index bea126c07b..0c00d44e21 100644 > --- a/target/riscv/insn_trans/trans_rvv.inc.c > +++ b/target/riscv/insn_trans/trans_rvv.inc.c > @@ -1986,3 +1986,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > return false; \ > } > GEN_OPFV_TRANS(vfsqrt_v, opfv_check) > + > +/* Vector Floating-Point MIN/MAX Instructions */ > +GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) > +GEN_OPFVV_TRANS(vfmax_vv, opfvv_check) > +GEN_OPFVF_TRANS(vfmin_vf, opfvf_check) > +GEN_OPFVF_TRANS(vfmax_vf, opfvf_check) > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 342ba0c196..f80b522c47 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -3768,3 +3768,30 @@ RVVCALL(OPFVV1, vfsqrt_v_d, OP_UU_D, H8, H8, float64_sqrt) > GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2, clearh) > GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4, clearl) > GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8, clearq) > + > +/* Vector Floating-Point MIN/MAX Instructions */ > +RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum) > +RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum) > +RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum) > +GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2, clearh) > +GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4, clearl) > +GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8, clearq) > +RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum) > +RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum) > +RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum) > +GEN_VEXT_VF(vfmin_vf_h, 2, 2, clearh) > +GEN_VEXT_VF(vfmin_vf_w, 4, 4, clearl) > +GEN_VEXT_VF(vfmin_vf_d, 8, 8, clearq) > + > +RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum) > +RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum) > +RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum) > +GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2, clearh) > +GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4, clearl) > +GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8, clearq) > +RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum) > +RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum) > +RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum) > +GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh) > +GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl) > +GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq) > -- > 2.23.0 >