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From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Palmer Dabbelt <palmer@sifive.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v4 24/28] riscv: sifive: Implement a model for SiFive FU540 OTP
Date: Thu, 22 Aug 2019 15:41:31 -0700
Message-ID: <CAKmqyKMLqA=+X6p2eLS77gH_TTVg7zDw2XAduOF4FQBHSTWryQ@mail.gmail.com> (raw)
In-Reply-To: <1566191521-7820-25-git-send-email-bmeng.cn@gmail.com>

On Sun, Aug 18, 2019 at 10:19 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> This implements a simple model for SiFive FU540 OTP (One-Time
> Programmable) Memory interface, primarily for reading out the
> stored serial number from the first 1 KiB of the 16 KiB OTP
> memory reserved by SiFive for internal use.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
> Changes in v4:
> - prefix all macros/variables/functions with SIFIVE_U/sifive_u
>   in the sifive_u_otp driver
>
> Changes in v3: None
> Changes in v2: None
>
>  hw/riscv/Makefile.objs          |   1 +
>  hw/riscv/sifive_u_otp.c         | 194 ++++++++++++++++++++++++++++++++++++++++
>  include/hw/riscv/sifive_u_otp.h |  90 +++++++++++++++++++
>  3 files changed, 285 insertions(+)
>  create mode 100644 hw/riscv/sifive_u_otp.c
>  create mode 100644 include/hw/riscv/sifive_u_otp.h
>
> diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
> index b95bbd5..fc3c6dd 100644
> --- a/hw/riscv/Makefile.objs
> +++ b/hw/riscv/Makefile.objs
> @@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o
>  obj-$(CONFIG_SIFIVE) += sifive_plic.o
>  obj-$(CONFIG_SIFIVE) += sifive_test.o
>  obj-$(CONFIG_SIFIVE_U) += sifive_u.o
> +obj-$(CONFIG_SIFIVE_U) += sifive_u_otp.o
>  obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o
>  obj-$(CONFIG_SIFIVE) += sifive_uart.o
>  obj-$(CONFIG_SPIKE) += spike.o
> diff --git a/hw/riscv/sifive_u_otp.c b/hw/riscv/sifive_u_otp.c
> new file mode 100644
> index 0000000..de8801c
> --- /dev/null
> +++ b/hw/riscv/sifive_u_otp.c
> @@ -0,0 +1,194 @@
> +/*
> + * QEMU SiFive U OTP (One-Time Programmable) Memory interface
> + *
> + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
> + *
> + * Simple model of the OTP to emulate register reads made by the SDK BSP
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "qemu/module.h"
> +#include "target/riscv/cpu.h"
> +#include "hw/riscv/sifive_u_otp.h"
> +
> +static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
> +{
> +    SiFiveUOTPState *s = opaque;
> +
> +    switch (addr) {
> +    case SIFIVE_U_OTP_PA:
> +        return s->pa;
> +    case SIFIVE_U_OTP_PAIO:
> +        return s->paio;
> +    case SIFIVE_U_OTP_PAS:
> +        return s->pas;
> +    case SIFIVE_U_OTP_PCE:
> +        return s->pce;
> +    case SIFIVE_U_OTP_PCLK:
> +        return s->pclk;
> +    case SIFIVE_U_OTP_PDIN:
> +        return s->pdin;
> +    case SIFIVE_U_OTP_PDOUT:
> +        if ((s->pce & SIFIVE_U_OTP_PCE_EN) &&
> +            (s->pdstb & SIFIVE_U_OTP_PDSTB_EN) &&
> +            (s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) {
> +            return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK];
> +        } else {
> +            return 0xff;
> +        }
> +    case SIFIVE_U_OTP_PDSTB:
> +        return s->pdstb;
> +    case SIFIVE_U_OTP_PPROG:
> +        return s->pprog;
> +    case SIFIVE_U_OTP_PTC:
> +        return s->ptc;
> +    case SIFIVE_U_OTP_PTM:
> +        return s->ptm;
> +    case SIFIVE_U_OTP_PTM_REP:
> +        return s->ptm_rep;
> +    case SIFIVE_U_OTP_PTR:
> +        return s->ptr;
> +    case SIFIVE_U_OTP_PTRIM:
> +        return s->ptrim;
> +    case SIFIVE_U_OTP_PWE:
> +        return s->pwe;
> +    }
> +
> +    hw_error("%s: read: addr=0x%x\n", __func__, (int)addr);

This should be qem_log_mask().

> +    return 0;
> +}
> +
> +static void sifive_u_otp_write(void *opaque, hwaddr addr,
> +                               uint64_t val64, unsigned int size)
> +{
> +    SiFiveUOTPState *s = opaque;
> +
> +    switch (addr) {
> +    case SIFIVE_U_OTP_PA:
> +        s->pa = (uint32_t) val64 & SIFIVE_U_OTP_PA_MASK;
> +        break;
> +    case SIFIVE_U_OTP_PAIO:
> +        s->paio = (uint32_t) val64;
> +        break;
> +    case SIFIVE_U_OTP_PAS:
> +        s->pas = (uint32_t) val64;
> +        break;
> +    case SIFIVE_U_OTP_PCE:
> +        s->pce = (uint32_t) val64;
> +        break;
> +    case SIFIVE_U_OTP_PCLK:
> +        s->pclk = (uint32_t) val64;
> +        break;
> +    case SIFIVE_U_OTP_PDIN:
> +        s->pdin = (uint32_t) val64;
> +        break;
> +    case SIFIVE_U_OTP_PDOUT:
> +        /* read-only */
> +        break;
> +    case SIFIVE_U_OTP_PDSTB:
> +        s->pdstb = (uint32_t) val64;
> +        break;
> +    case SIFIVE_U_OTP_PPROG:
> +        s->pprog = (uint32_t) val64;
> +        break;
> +    case SIFIVE_U_OTP_PTC:
> +        s->ptc = (uint32_t) val64;
> +        break;
> +    case SIFIVE_U_OTP_PTM:
> +        s->ptm = (uint32_t) val64;
> +        break;
> +    case SIFIVE_U_OTP_PTM_REP:
> +        s->ptm_rep = (uint32_t) val64;
> +        break;
> +    case SIFIVE_U_OTP_PTR:
> +        s->ptr = (uint32_t) val64;
> +        break;
> +    case SIFIVE_U_OTP_PTRIM:
> +        s->ptrim = (uint32_t) val64;
> +        break;
> +    case SIFIVE_U_OTP_PWE:
> +        s->pwe = (uint32_t) val64;
> +        break;
> +    default:
> +        hw_error("%s: bad write: addr=0x%x v=0x%x\n",
> +                 __func__, (int)addr, (int)val64);

Same as above

> +    }
> +}
> +
> +static const MemoryRegionOps sifive_u_otp_ops = {
> +    .read = sifive_u_otp_read,
> +    .write = sifive_u_otp_write,
> +    .endianness = DEVICE_NATIVE_ENDIAN,
> +    .valid = {
> +        .min_access_size = 4,
> +        .max_access_size = 4
> +    }
> +};
> +
> +static Property sifive_u_otp_properties[] = {
> +    DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0),
> +    DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
> +{
> +    SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
> +
> +    memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_otp_ops, s,
> +                          TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
> +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
> +
> +    /* Initialize all fuses' initial value to 0xFFs */
> +    memset(s->fuse, 0xff, sizeof(s->fuse));
> +
> +    /* Make a valid content of serial number */
> +    s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial;
> +    s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial);
> +}
> +
> +static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(klass);
> +
> +    dc->props = sifive_u_otp_properties;
> +    dc->realize = sifive_u_otp_realize;
> +}
> +
> +static const TypeInfo sifive_u_otp_info = {
> +    .name          = TYPE_SIFIVE_U_OTP,
> +    .parent        = TYPE_SYS_BUS_DEVICE,
> +    .instance_size = sizeof(SiFiveUOTPState),
> +    .class_init    = sifive_u_otp_class_init,
> +};
> +
> +static void sifive_u_otp_register_types(void)
> +{
> +    type_register_static(&sifive_u_otp_info);
> +}
> +
> +type_init(sifive_u_otp_register_types)
> +
> +
> +/* Create OTP device */
> +DeviceState *sifive_u_otp_create(hwaddr addr, uint32_t serial)

Don't include this function.

Alistair

> +{
> +    DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_U_OTP);
> +    qdev_prop_set_uint32(dev, "serial", serial);
> +    qdev_init_nofail(dev);
> +    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
> +
> +    return dev;
> +}
> diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/riscv/sifive_u_otp.h
> new file mode 100644
> index 0000000..7eac661
> --- /dev/null
> +++ b/include/hw/riscv/sifive_u_otp.h
> @@ -0,0 +1,90 @@
> +/*
> + * QEMU SiFive U OTP (One-Time Programmable) Memory interface
> + *
> + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef HW_SIFIVE_U_OTP_H
> +#define HW_SIFIVE_U_OTP_H
> +
> +enum {
> +    SIFIVE_U_OTP_PA         = 0x00,
> +    SIFIVE_U_OTP_PAIO       = 0x04,
> +    SIFIVE_U_OTP_PAS        = 0x08,
> +    SIFIVE_U_OTP_PCE        = 0x0C,
> +    SIFIVE_U_OTP_PCLK       = 0x10,
> +    SIFIVE_U_OTP_PDIN       = 0x14,
> +    SIFIVE_U_OTP_PDOUT      = 0x18,
> +    SIFIVE_U_OTP_PDSTB      = 0x1C,
> +    SIFIVE_U_OTP_PPROG      = 0x20,
> +    SIFIVE_U_OTP_PTC        = 0x24,
> +    SIFIVE_U_OTP_PTM        = 0x28,
> +    SIFIVE_U_OTP_PTM_REP    = 0x2C,
> +    SIFIVE_U_OTP_PTR        = 0x30,
> +    SIFIVE_U_OTP_PTRIM      = 0x34,
> +    SIFIVE_U_OTP_PWE        = 0x38
> +};
> +
> +enum {
> +    SIFIVE_U_OTP_PCE_EN     = (1 << 0)
> +};
> +
> +enum {
> +    SIFIVE_U_OTP_PDSTB_EN   = (1 << 0)
> +};
> +
> +enum {
> +    SIFIVE_U_OTP_PTRIM_EN   = (1 << 0)
> +};
> +
> +#define SIFIVE_U_OTP_PA_MASK        0xfff
> +#define SIFIVE_U_OTP_NUM_FUSES      0x1000
> +#define SIFIVE_U_OTP_SERIAL_ADDR    0xfc
> +
> +#define SIFIVE_U_OTP_REG_SIZE       0x1000
> +
> +#define TYPE_SIFIVE_U_OTP           "riscv.sifive.u.otp"
> +
> +#define SIFIVE_U_OTP(obj) \
> +    OBJECT_CHECK(SiFiveUOTPState, (obj), TYPE_SIFIVE_U_OTP)
> +
> +typedef struct SiFiveUOTPState {
> +    /*< private >*/
> +    SysBusDevice parent_obj;
> +
> +    /*< public >*/
> +    MemoryRegion mmio;
> +    uint32_t pa;
> +    uint32_t paio;
> +    uint32_t pas;
> +    uint32_t pce;
> +    uint32_t pclk;
> +    uint32_t pdin;
> +    uint32_t pdstb;
> +    uint32_t pprog;
> +    uint32_t ptc;
> +    uint32_t ptm;
> +    uint32_t ptm_rep;
> +    uint32_t ptr;
> +    uint32_t ptrim;
> +    uint32_t pwe;
> +    uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES];
> +    /* config */
> +    uint32_t serial;
> +} SiFiveUOTPState;
> +
> +DeviceState *sifive_u_otp_create(hwaddr addr, uint32_t serial);
> +
> +#endif /* HW_SIFIVE_U_OTP_H */
> --
> 2.7.4
>
>


  reply index

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-19  5:11 [Qemu-devel] [PATCH v4 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 01/28] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 03/28] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 04/28] riscv: hw: Change create_fdt() to return void Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-08-19 20:08   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-08-22 22:40   ` Alistair Francis
2019-08-23  1:57     ` Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 15/28] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 16/28] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 17/28] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-08-19 20:21   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-08-19 20:22   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 19/28] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-08-20 18:26   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 21/28] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 22/28] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 23/28] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 24/28] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-08-22 22:41   ` Alistair Francis [this message]
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 25/28] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 26/28] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-08-19  5:12 ` [Qemu-devel] [PATCH v4 27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-08-22 22:39   ` Alistair Francis
2019-08-19  5:12 ` [Qemu-devel] [PATCH v4 28/28] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng

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