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Mon, 22 Nov 2021 22:12:04 -0800 (PST) MIME-Version: 1.0 References: <20211112145902.205131-1-frederic.petrot@univ-grenoble-alpes.fr> <20211112145902.205131-5-frederic.petrot@univ-grenoble-alpes.fr> In-Reply-To: <20211112145902.205131-5-frederic.petrot@univ-grenoble-alpes.fr> From: Alistair Francis Date: Tue, 23 Nov 2021 16:11:38 +1000 Message-ID: Subject: Re: [PATCH v5 04/18] target/riscv: additional macros to check instruction support To: =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::d31 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::d31; envelope-from=alistair23@gmail.com; helo=mail-io1-xd31.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Bin Meng , Richard Henderson , "qemu-devel@nongnu.org Developers" , Alistair Francis , Fabien Portas , Palmer Dabbelt , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sat, Nov 13, 2021 at 1:08 AM Fr=C3=A9d=C3=A9ric P=C3=A9trot wrote: > > Given that the 128-bit version of the riscv spec adds new instructions, a= nd > that some instructions that were previously only available in 64-bit mode > are now available for both 64-bit and 128-bit, we added new macros to che= ck > for the processor mode during translation. > Although RV128 is a superset of RV64, we keep for now the RV64 only tests > for extensions other than RVI and RVM. > > Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot > Co-authored-by: Fabien Portas > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/translate.c | 20 ++++++++++++++++---- > 1 file changed, 16 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 1d57bc97b5..d98bde9b6b 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -368,10 +368,22 @@ EX_SH(12) > } \ > } while (0) > > -#define REQUIRE_64BIT(ctx) do { \ > - if (get_xl(ctx) < MXL_RV64) { \ > - return false; \ > - } \ > +#define REQUIRE_64BIT(ctx) do { \ > + if (get_xl(ctx) !=3D MXL_RV64) { \ > + return false; \ > + } \ > +} while (0) > + > +#define REQUIRE_128BIT(ctx) do { \ > + if (get_xl(ctx) !=3D MXL_RV128) { \ > + return false; \ > + } \ > +} while (0) > + > +#define REQUIRE_64_OR_128BIT(ctx) do { \ > + if (get_xl(ctx) =3D=3D MXL_RV32) { \ > + return false; \ > + } \ > } while (0) > > static int ex_rvc_register(DisasContext *ctx, int reg) > -- > 2.33.1 > >