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Tue, 16 Mar 2021 13:18:11 -0700 (PDT) MIME-Version: 1.0 References: <20210311103005.1400718-1-georg.kotheimer@kernkonzept.com> In-Reply-To: <20210311103005.1400718-1-georg.kotheimer@kernkonzept.com> From: Alistair Francis Date: Tue, 16 Mar 2021 16:16:35 -0400 Message-ID: Subject: Re: [PATCH] target/riscv: Adjust privilege level for HLV(X)/HSV instructions To: Georg Kotheimer Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::734; envelope-from=alistair23@gmail.com; helo=mail-qk1-x734.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Mar 11, 2021 at 5:32 AM Georg Kotheimer wrote: > > According to the specification the "field SPVP of hstatus controls the > privilege level of the access" for the hypervisor virtual-machine load > and store instructions HLV, HLVX and HSV. > > Signed-off-by: Georg Kotheimer Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu_helper.c | 25 ++++++++++++++----------- > 1 file changed, 14 insertions(+), 11 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 2f43939fb6..d0577b1e08 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -325,7 +325,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, > use_background = true; > } > > - if (mode == PRV_M && access_type != MMU_INST_FETCH) { > + /* MPRV does not affect the virtual-machine load/store > + instructions, HLV, HLVX, and HSV. */ > + if (riscv_cpu_two_stage_lookup(mmu_idx)) { > + mode = get_field(env->hstatus, HSTATUS_SPVP); > + } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { > if (get_field(env->mstatus, MSTATUS_MPRV)) { > mode = get_field(env->mstatus, MSTATUS_MPP); > } > @@ -695,19 +699,18 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", > __func__, address, access_type, mmu_idx); > > - if (mode == PRV_M && access_type != MMU_INST_FETCH) { > - if (get_field(env->mstatus, MSTATUS_MPRV)) { > - mode = get_field(env->mstatus, MSTATUS_MPP); > + /* MPRV does not affect the virtual-machine load/store > + instructions, HLV, HLVX, and HSV. */ > + if (riscv_cpu_two_stage_lookup(mmu_idx)) { > + mode = get_field(env->hstatus, HSTATUS_SPVP); > + } else if (mode == PRV_M && access_type != MMU_INST_FETCH && > + get_field(env->mstatus, MSTATUS_MPRV)) { > + mode = get_field(env->mstatus, MSTATUS_MPP); > + if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { > + two_stage_lookup = true; > } > } > > - if (riscv_has_ext(env, RVH) && env->priv == PRV_M && > - access_type != MMU_INST_FETCH && > - get_field(env->mstatus, MSTATUS_MPRV) && > - get_field(env->mstatus, MSTATUS_MPV)) { > - two_stage_lookup = true; > - } > - > if (riscv_cpu_virt_enabled(env) || > ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && > access_type != MMU_INST_FETCH)) { > -- > 2.30.1 > >