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From: Alistair Francis <alistair23@gmail.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Bin Meng <bin.meng@windriver.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Max Hsu <max.hsu@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [PATCH RESEND v2 4/4] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer
Date: Tue, 14 Sep 2021 12:24:34 +1000	[thread overview]
Message-ID: <CAKmqyKMY_7jJ2g9Te8JRPD0dwMP_y1WPnjZkKc5Fj+iJhWiRig@mail.gmail.com> (raw)
In-Reply-To: <20210912130553.179501-5-frank.chang@sifive.com>

On Sun, Sep 12, 2021 at 11:11 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Real PDMA doesn't set Control.error if there are 0 bytes to be
> transferred. The DMA transfer is still success.
>
> The following result is PDMA tested in U-Boot on Unmatched board:
>
> => mw.l 0x3000000 0x0                      <= Disclaim channel 0
> => mw.l 0x3000000 0x1                      <= Claim channel 0
> => mw.l 0x3000004 0x55000000               <= wsize = rsize = 5 (2^5 = 32 bytes)
> => mw.q 0x3000008 0x0                      <= NextBytes = 0
> => mw.q 0x3000010 0x84000000               <= NextDestination = 0x84000000
> => mw.q 0x3000018 0x84001000               <= NextSource = 0x84001000
> => mw.l 0x84000000 0x87654321              <= Fill test data to dst
> => mw.l 0x84001000 0x12345678              <= Fill test data to src
> => md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
> 84000000: 87654321                               !Ce.
> 84001000: 12345678                               xV4.
> => md.l 0x3000000 8                        <= Dump PDMA status
> 03000000: 00000001 55000000 00000000 00000000    .......U........
> 03000010: 84000000 00000000 84001000 00000000    ................
> => mw.l 0x3000000 0x3                      <= Set channel 0 run and claim bits
> => md.l 0x3000000 8                        <= Dump PDMA status
> 03000000: 40000001 55000000 00000000 00000000    ...@...U........
> 03000010: 84000000 00000000 84001000 00000000    ................
> => md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
> 84000000: 87654321                               !Ce.
> 84001000: 12345678                               xV4.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Tested-by: Max Hsu <max.hsu@sifive.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Bin Meng <bmeng.cn@gmail.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  hw/dma/sifive_pdma.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
> index d7d2c53e97e..b4fd40573a5 100644
> --- a/hw/dma/sifive_pdma.c
> +++ b/hw/dma/sifive_pdma.c
> @@ -80,7 +80,7 @@ static void sifive_pdma_run(SiFivePDMAState *s, int ch)
>
>      /* do nothing if bytes to transfer is zero */
>      if (!bytes) {
> -        goto error;
> +        goto done;
>      }
>
>      /*
> @@ -135,11 +135,6 @@ static void sifive_pdma_run(SiFivePDMAState *s, int ch)
>          s->chan[ch].exec_bytes -= remainder;
>      }
>
> -    /* indicate a DMA transfer is done */
> -    s->chan[ch].state = DMA_CHAN_STATE_DONE;
> -    s->chan[ch].control &= ~CONTROL_RUN;
> -    s->chan[ch].control |= CONTROL_DONE;
> -
>      /* reload exec_ registers if repeat is required */
>      if (s->chan[ch].next_config & CONFIG_REPEAT) {
>          s->chan[ch].exec_bytes = bytes;
> @@ -147,6 +142,11 @@ static void sifive_pdma_run(SiFivePDMAState *s, int ch)
>          s->chan[ch].exec_src = src;
>      }
>
> +done:
> +    /* indicate a DMA transfer is done */
> +    s->chan[ch].state = DMA_CHAN_STATE_DONE;
> +    s->chan[ch].control &= ~CONTROL_RUN;
> +    s->chan[ch].control |= CONTROL_DONE;
>      return;
>
>  error:
> --
> 2.25.1
>
>


      reply	other threads:[~2021-09-14  2:26 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-12 13:05 [PATCH RESEND v2 0/4] hw/dma: Align SiFive PDMA behavior with real hardware frank.chang
2021-09-12 13:05 ` [PATCH RESEND v2 1/4] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set frank.chang
2021-09-12 13:05 ` [PATCH RESEND v2 2/4] hw/dma: sifive_pdma: claim bit must be set before DMA transactions frank.chang
2021-09-12 13:05 ` [PATCH RESEND v2 3/4] hw/dma: sifive_pdma: allow non-multiple transaction size transactions frank.chang
2021-09-12 13:05 ` [PATCH RESEND v2 4/4] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer frank.chang
2021-09-14  2:24   ` Alistair Francis [this message]

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