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That's all we know. X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , "open list:RISC-V" , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "qemu-devel@nongnu.org Developers" , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Aug 14, 2020 at 9:41 AM Bin Meng wrote: > > From: Bin Meng > > RISC-V machines do not instantiate RISC-V CPUs directly, instead > they do that via the hart array. Add a new property for the reset > vector address to allow the value to be passed to the CPU, before > CPU is realized. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > hw/riscv/riscv_hart.c | 3 +++ > include/hw/riscv/riscv_hart.h | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c > index f59fe52..613ea2a 100644 > --- a/hw/riscv/riscv_hart.c > +++ b/hw/riscv/riscv_hart.c > @@ -31,6 +31,8 @@ static Property riscv_harts_props[] = { > DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), > DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), > DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), > + DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, > + DEFAULT_RSTVEC), > DEFINE_PROP_END_OF_LIST(), > }; > > @@ -44,6 +46,7 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, > char *cpu_type, Error **errp) > { > object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type); > + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); > s->harts[idx].env.mhartid = s->hartid_base + idx; > qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); > return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); > diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h > index c75856f..77aa4bc 100644 > --- a/include/hw/riscv/riscv_hart.h > +++ b/include/hw/riscv/riscv_hart.h > @@ -37,6 +37,7 @@ typedef struct RISCVHartArrayState { > uint32_t num_harts; > uint32_t hartid_base; > char *cpu_type; > + uint64_t resetvec; > RISCVCPU *harts; > } RISCVHartArrayState; > > -- > 2.7.4 > >