[Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions

[Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions

[Alistair Francis]

Based-on: <cover.1555726824.git.alistair.francis@wdc.com>

Now that the RISC-V spec has started to be ratified let's update our
QEMU implementation. There are a few things going on here:
 - Add priv version 1.11.0 to QEMU
    - This is the ratified version of the Privledge spec
    - There are almost no changes to 1.10
 - Mark the 1.09.1 privledge spec as depreated
     - Let's aim to remove it in two releases
 - Set priv version 1.11.0 as the default
 - Remove the user_spec version
     - This doesn't really mean anything so let's remove it
 - Add support for the "Counters" extension
 - Add command line options for Zifencei and Zicsr

We can remove the spec version as it's unused and has never been exposed
to users. The idea is to match the specs in specifying the version. To
handle versions in the future we can extend the extension props to
handle version information.

For example something like this: -cpu rv64,i=2.2,c=2.0,h=0.4,priv_spec=1.11

NOTE: This isn't supported today as we only have one of each version.

This will be a future change if we decide to support multiple versions
of extensions.

The "priv_spec" string doesn't really match, but I don't have a better
way to say "Machine ISA" and "Supervisor ISA" which is what is included
in "priv_spec".

For completeness I have also added the Counters, Zifencei and Zicsr
extensions.

Everything else seems to match the spec names/style.

Please let me know if I'm missing something. QEMU 4.1 is the first
release to support the extensions from the command line, so we can
easily change it until then. After that it'll take more work to change
the command line interface.

Alistair Francis (9):
  target/riscv: Restructure deprecatd CPUs
  target/riscv: Add the privledge spec version 1.11.0
  target/riscv: Comment in the mcountinhibit CSR
  target/riscv: Set privledge spec 1.11.0 as default
  qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1
  target/riscv: Require either I or E base extension
  target/riscv: Remove user version information
  target/riscv: Add support for disabling/enabling Counters
  target/riscv: Add Zifencei and Zicsr as command line options

 qemu-deprecated.texi                          |  8 +++
 target/riscv/cpu.c                            | 72 ++++++++++---------
 target/riscv/cpu.h                            | 19 ++---
 target/riscv/cpu_bits.h                       |  1 +
 target/riscv/csr.c                            | 13 +++-
 .../riscv/insn_trans/trans_privileged.inc.c   |  2 +-
 6 files changed, 71 insertions(+), 44 deletions(-)

-- 
2.22.0

[Qemu-devel] [PATCH v1 1/9] target/riscv: Restructure deprecatd CPUs

[Alistair Francis]

Restructure the deprecated CPUs to make it clear in the code that these
are depreated. They are already marked as deprecated in
qemu-deprecated.texi. There are no functional changes.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 18 ++++++++++--------
 target/riscv/cpu.h | 13 +++++++------
 2 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0632ac08cf..a4dd7ae6fc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -558,18 +558,20 @@ static const TypeInfo riscv_cpu_type_infos[] = {
     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
 #if defined(TARGET_RISCV32)
     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base32_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32imacu_nommu_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init)
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init),
+    /* Depreacted */
+    DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
 #elif defined(TARGET_RISCV64)
     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base64_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64imacu_nommu_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init)
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init),
+    /* Deprecated */
+    DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
 #endif
 };
 
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b47cde5017..1668d12018 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -35,16 +35,17 @@
 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
-#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
-#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
-#define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
-#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
-#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
-#define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
+/* Deprecated */
+#define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
+#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
+#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
+#define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
+#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
+#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
 
 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
-- 
2.22.0

[Qemu-devel] [PATCH v1 2/9] target/riscv: Add the privledge spec version 1.11.0

[Alistair Francis]

Add support for the ratified RISC-V privledge spec.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                             | 1 +
 target/riscv/insn_trans/trans_privileged.inc.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1668d12018..4e58c3b856 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,6 +81,7 @@ enum {
 #define USER_VERSION_2_02_0 0x00020200
 #define PRIV_VERSION_1_09_1 0x00010901
 #define PRIV_VERSION_1_10_0 0x00011000
+#define PRIV_VERSION_1_11_0 0x00011100
 
 #define TRANSLATE_FAIL 1
 #define TRANSLATE_SUCCESS 0
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
index 664d6ba3f2..c5e4b3e49a 100644
--- a/target/riscv/insn_trans/trans_privileged.inc.c
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -90,7 +90,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
 static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
 {
 #ifndef CONFIG_USER_ONLY
-    if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
+    if (ctx->priv_ver >= PRIV_VERSION_1_10_0) {
         gen_helper_tlb_flush(cpu_env);
         return true;
     }
-- 
2.22.0

[Qemu-devel] [PATCH v1 3/9] target/riscv: Comment in the mcountinhibit CSR

[Alistair Francis]

Add a comment for the new mcountinhibit which conflicts with the
CSR_MUCOUNTEREN from version 1.09.1. This can be updated when we remove
1.09.1.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 1 +
 target/riscv/csr.c      | 6 ++++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 47450a3cdb..11f971ad5d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -136,6 +136,7 @@
 #define CSR_MCOUNTEREN      0x306
 
 /* Legacy Counter Setup (priv v1.9.1) */
+/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
 #define CSR_MUCOUNTEREN     0x320
 #define CSR_MSCOUNTEREN     0x321
 #define CSR_MHCOUNTEREN     0x322
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c67d29e206..437387fd28 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -461,18 +461,20 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
 {
-    if (env->priv_ver > PRIV_VERSION_1_09_1) {
+    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
         return -1;
     }
     *val = env->mcounteren;
     return 0;
 }
 
+/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
 {
-    if (env->priv_ver > PRIV_VERSION_1_09_1) {
+    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
         return -1;
     }
     env->mcounteren = val;
-- 
2.22.0

[Qemu-devel] [PATCH v1 4/9] target/riscv: Set privledge spec 1.11.0 as default

[Alistair Francis]

Set the priv spec version 1.11.0 as the default and allow selecting it
via the command line.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a4dd7ae6fc..a23d83921a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -111,7 +111,7 @@ static void riscv_any_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
-    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
+    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_11_0);
     set_resetvec(env, DEFAULT_RSTVEC);
 }
 
@@ -316,7 +316,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     RISCVCPU *cpu = RISCV_CPU(dev);
     CPURISCVState *env = &cpu->env;
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
-    int priv_version = PRIV_VERSION_1_10_0;
+    int priv_version = PRIV_VERSION_1_11_0;
     int user_version = USER_VERSION_2_02_0;
     target_ulong target_misa = 0;
     Error *local_err = NULL;
@@ -328,7 +328,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     }
 
     if (cpu->cfg.priv_spec) {
-        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
+        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
+            priv_version = PRIV_VERSION_1_11_0;
+        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
             priv_version = PRIV_VERSION_1_10_0;
         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
             priv_version = PRIV_VERSION_1_09_1;
-- 
2.22.0

[Qemu-devel] [PATCH v1 5/9] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1

[Alistair Francis]

Deprecate the RISC-V privledge spec version 1.09.1 in favour of the new
1.10.0 and the ratified 1.11.0.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 qemu-deprecated.texi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
index 50292d820b..b1111debf7 100644
--- a/qemu-deprecated.texi
+++ b/qemu-deprecated.texi
@@ -138,6 +138,14 @@ The ``acl_show'', ``acl_reset'', ``acl_policy'', ``acl_add'', and
 ``acl_remove'' commands are deprecated with no replacement. Authorization
 for VNC should be performed using the pluggable QAuthZ objects.
 
+@section Guest Emulator ISAs
+
+@subsection RISC-V ISA privledge specification version 1.09.1 (since 4.1)
+
+The RISC-V ISA privledge specification version 1.09.1 has been deprecated.
+QEMU supports both the newer version 1.10.0 and the ratified version 1.11.0, these
+should be used instead of the 1.09.1 version.
+
 @section System emulator CPUS
 
 @subsection RISC-V ISA CPUs (since 4.1)
-- 
2.22.0

[Qemu-devel] [PATCH v1 6/9] target/riscv: Require either I or E base extension

[Alistair Francis]

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a23d83921a..21bfaa9722 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -373,6 +373,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
                        return;
        }
 
+        if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
+            error_setg(errp,
+                       "Either I or E extension must be set");
+                       return;
+       }
+
        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
                                cpu->cfg.ext_a & cpu->cfg.ext_f &
                                cpu->cfg.ext_d)) {
-- 
2.22.0

[Qemu-devel] [PATCH v1 7/9] target/riscv: Remove user version information

[Alistair Francis]

Remove the user version information. This was never used and never
publically exposed in a release of QEMU, so let's just remove it. In
future to manage versions we can extend the extension properties to
specify version.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 32 +++++++++-----------------------
 target/riscv/cpu.h |  2 --
 2 files changed, 9 insertions(+), 25 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 21bfaa9722..ddbe922958 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -89,9 +89,8 @@ static void set_misa(CPURISCVState *env, target_ulong misa)
     env->misa_mask = env->misa = misa;
 }
 
-static void set_versions(CPURISCVState *env, int user_ver, int priv_ver)
+static void set_priv_version(CPURISCVState *env, int priv_ver)
 {
-    env->user_ver = user_ver;
     env->priv_ver = priv_ver;
 }
 
@@ -111,7 +110,7 @@ static void riscv_any_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
-    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_11_0);
+    set_priv_version(env, PRIV_VERSION_1_11_0);
     set_resetvec(env, DEFAULT_RSTVEC);
 }
 
@@ -128,7 +127,7 @@ static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
-    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1);
+    set_priv_version(env, PRIV_VERSION_1_09_1);
     set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_MMU);
     set_feature(env, RISCV_FEATURE_PMP);
@@ -138,7 +137,7 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
-    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
     set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_MMU);
     set_feature(env, RISCV_FEATURE_PMP);
@@ -148,7 +147,7 @@ static void rv32imacu_nommu_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
-    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
     set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_PMP);
 }
@@ -166,7 +165,7 @@ static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
-    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1);
+    set_priv_version(env, PRIV_VERSION_1_09_1);
     set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_MMU);
     set_feature(env, RISCV_FEATURE_PMP);
@@ -176,7 +175,7 @@ static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
-    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
     set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_MMU);
     set_feature(env, RISCV_FEATURE_PMP);
@@ -186,7 +185,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
-    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
     set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_PMP);
 }
@@ -317,7 +316,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     CPURISCVState *env = &cpu->env;
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
     int priv_version = PRIV_VERSION_1_11_0;
-    int user_version = USER_VERSION_2_02_0;
     target_ulong target_misa = 0;
     Error *local_err = NULL;
 
@@ -342,18 +340,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         }
     }
 
-    if (cpu->cfg.user_spec) {
-        if (!g_strcmp0(cpu->cfg.user_spec, "v2.02.0")) {
-            user_version = USER_VERSION_2_02_0;
-        } else {
-            error_setg(errp,
-                       "Unsupported user spec version '%s'",
-                       cpu->cfg.user_spec);
-            return;
-        }
-    }
-
-    set_versions(env, user_version, priv_version);
+    set_priv_version(env, priv_version);
     set_resetvec(env, DEFAULT_RSTVEC);
 
     if (cpu->cfg.mmu) {
@@ -454,7 +441,6 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
-    DEFINE_PROP_STRING("user_spec", RISCVCPU, cfg.user_spec),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
     DEFINE_PROP_END_OF_LIST(),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4e58c3b856..a558c353f0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -78,7 +78,6 @@ enum {
     RISCV_FEATURE_MISA
 };
 
-#define USER_VERSION_2_02_0 0x00020200
 #define PRIV_VERSION_1_09_1 0x00010901
 #define PRIV_VERSION_1_10_0 0x00011000
 #define PRIV_VERSION_1_11_0 0x00011100
@@ -104,7 +103,6 @@ struct CPURISCVState {
 
     target_ulong badaddr;
 
-    target_ulong user_ver;
     target_ulong priv_ver;
     target_ulong misa;
     target_ulong misa_mask;
-- 
2.22.0

[Qemu-devel] [PATCH v1 8/9] target/riscv: Add support for disabling/enabling Counters

[Alistair Francis]

Add support for disabling/enabling the "Counters" extension.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 1 +
 target/riscv/cpu.h | 1 +
 target/riscv/csr.c | 7 +++++++
 3 files changed, 9 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ddbe922958..5af1c9b38c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -440,6 +440,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a558c353f0..786f620564 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -221,6 +221,7 @@ typedef struct RISCVCPU {
         bool ext_c;
         bool ext_s;
         bool ext_u;
+        bool ext_counters;
 
         char *priv_spec;
         char *user_spec;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 437387fd28..a9aa8ab1b5 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -56,8 +56,15 @@ static int fs(CPURISCVState *env, int csrno)
 static int ctr(CPURISCVState *env, int csrno)
 {
 #if !defined(CONFIG_USER_ONLY)
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
     uint32_t ctr_en = ~0u;
 
+    if (!cpu->cfg.ext_counters) {
+        /* The Counters extensions is not enabled */
+        return -1;
+    }
+
     if (env->priv < PRV_M) {
         ctr_en &= env->mcounteren;
     }
-- 
2.22.0

[Qemu-devel] [PATCH v1 9/9] target/riscv: Add Zifencei and Zicsr as command line options

[Alistair Francis]

For completeness let's add Zifencei and Zicsr as command line options,
even though they can't be disabled at the moment.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 9 +++++++++
 target/riscv/cpu.h | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5af1c9b38c..53cf8607f7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -409,6 +409,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         set_misa(env, RVXLEN | target_misa);
     }
 
+    if (!cpu->cfg.ext_ifencei) {
+        warn_report("QEMU does not support disabling Zifencei");
+    }
+    if (!cpu->cfg.ext_icsr) {
+        warn_report("QEMU does not support disabling Zicsr");
+    }
+
     riscv_cpu_register_gdb_regs_for_features(cs);
 
     qemu_init_vcpu(cs);
@@ -441,6 +448,8 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 786f620564..b4c212dfcf 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -222,6 +222,8 @@ typedef struct RISCVCPU {
         bool ext_s;
         bool ext_u;
         bool ext_counters;
+        bool ext_ifencei;
+        bool ext_icsr;
 
         char *priv_spec;
         char *user_spec;
-- 
2.22.0

Re: [Qemu-devel] [PATCH v1 1/9] target/riscv: Restructure deprecatd CPUs

[Philippe Mathieu-Daudé]

On 6/18/19 3:31 AM, Alistair Francis wrote:
> Restructure the deprecated CPUs to make it clear in the code that these
> are depreated. They are already marked as deprecated in
> qemu-deprecated.texi. There are no functional changes.
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu.c | 18 ++++++++++--------
>  target/riscv/cpu.h | 13 +++++++------
>  2 files changed, 17 insertions(+), 14 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0632ac08cf..a4dd7ae6fc 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -558,18 +558,20 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>      DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
>  #if defined(TARGET_RISCV32)
>      DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base32_cpu_init),
> -    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
> -    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init),
> -    DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init),
>      DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32imacu_nommu_cpu_init),
> -    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init)
> +    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init),
> +    /* Depreacted */

"Deprecated" in patch subject and here ;)

> +    DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init),
> +    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
> +    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
>  #elif defined(TARGET_RISCV64)
>      DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base64_cpu_init),
> -    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
> -    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init),
> -    DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),
>      DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64imacu_nommu_cpu_init),
> -    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init)
> +    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init),
> +    /* Deprecated */
> +    DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),
> +    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
> +    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
>  #endif
>  };
>  
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index b47cde5017..1668d12018 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -35,16 +35,17 @@
>  #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
>  #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
>  #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
> -#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
> -#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
> -#define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
> -#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
> -#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
> -#define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
>  #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
>  #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
>  #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
>  #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
> +/* Deprecated */
> +#define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
> +#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
> +#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
> +#define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
> +#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
> +#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
>  
>  #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
>  #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
> 

Re: [Qemu-devel] [PATCH v1 1/9] target/riscv: Restructure deprecatd CPUs

[Alistair Francis]

On Mon, Jun 17, 2019 at 10:23 PM Philippe Mathieu-Daudé
<philmd@redhat.com> wrote:
>
> On 6/18/19 3:31 AM, Alistair Francis wrote:
> > Restructure the deprecated CPUs to make it clear in the code that these
> > are depreated. They are already marked as deprecated in
> > qemu-deprecated.texi. There are no functional changes.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >  target/riscv/cpu.c | 18 ++++++++++--------
> >  target/riscv/cpu.h | 13 +++++++------
> >  2 files changed, 17 insertions(+), 14 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 0632ac08cf..a4dd7ae6fc 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -558,18 +558,20 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> >      DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
> >  #if defined(TARGET_RISCV32)
> >      DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base32_cpu_init),
> > -    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
> > -    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init),
> > -    DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init),
> >      DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32imacu_nommu_cpu_init),
> > -    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init)
> > +    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init),
> > +    /* Depreacted */
>
> "Deprecated" in patch subject and here ;)

Thanks, fixed!

Alistair

>
> > +    DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init),
> > +    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
> > +    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
> >  #elif defined(TARGET_RISCV64)
> >      DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base64_cpu_init),
> > -    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
> > -    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init),
> > -    DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),
> >      DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64imacu_nommu_cpu_init),
> > -    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init)
> > +    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init),
> > +    /* Deprecated */
> > +    DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),
> > +    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
> > +    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
> >  #endif
> >  };
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index b47cde5017..1668d12018 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -35,16 +35,17 @@
> >  #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
> >  #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
> >  #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
> > -#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
> > -#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
> > -#define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
> > -#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
> > -#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
> > -#define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
> >  #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
> >  #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
> >  #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
> >  #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
> > +/* Deprecated */
> > +#define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
> > +#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
> > +#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
> > +#define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
> > +#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
> > +#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
> >
> >  #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
> >  #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
> >

Re: [Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions

[Palmer Dabbelt]

On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote:
> Based-on: <cover.1555726824.git.alistair.francis@wdc.com>
>
> Now that the RISC-V spec has started to be ratified let's update our
> QEMU implementation. There are a few things going on here:
>  - Add priv version 1.11.0 to QEMU
>     - This is the ratified version of the Privledge spec
>     - There are almost no changes to 1.10
>  - Mark the 1.09.1 privledge spec as depreated
>      - Let's aim to remove it in two releases
>  - Set priv version 1.11.0 as the default
>  - Remove the user_spec version
>      - This doesn't really mean anything so let's remove it
>  - Add support for the "Counters" extension
>  - Add command line options for Zifencei and Zicsr

Thanks!  I'll look at the code, but I've currently got this queued up behind
your hypervisor patches so it might take a bit.  LMK if you want me to invert
the priority on these.  I'll probably be buried until the start of July.

> We can remove the spec version as it's unused and has never been exposed
> to users. The idea is to match the specs in specifying the version. To
> handle versions in the future we can extend the extension props to
> handle version information.
>
> For example something like this: -cpu rv64,i=2.2,c=2.0,h=0.4,priv_spec=1.11
>
> NOTE: This isn't supported today as we only have one of each version.
>
> This will be a future change if we decide to support multiple versions
> of extensions.
>
> The "priv_spec" string doesn't really match, but I don't have a better
> way to say "Machine ISA" and "Supervisor ISA" which is what is included
> in "priv_spec".
>
> For completeness I have also added the Counters, Zifencei and Zicsr
> extensions.
>
> Everything else seems to match the spec names/style.
>
> Please let me know if I'm missing something. QEMU 4.1 is the first
> release to support the extensions from the command line, so we can
> easily change it until then. After that it'll take more work to change
> the command line interface.
>
> Alistair Francis (9):
>   target/riscv: Restructure deprecatd CPUs
>   target/riscv: Add the privledge spec version 1.11.0
>   target/riscv: Comment in the mcountinhibit CSR
>   target/riscv: Set privledge spec 1.11.0 as default
>   qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1
>   target/riscv: Require either I or E base extension
>   target/riscv: Remove user version information
>   target/riscv: Add support for disabling/enabling Counters
>   target/riscv: Add Zifencei and Zicsr as command line options
>
>  qemu-deprecated.texi                          |  8 +++
>  target/riscv/cpu.c                            | 72 ++++++++++---------
>  target/riscv/cpu.h                            | 19 ++---
>  target/riscv/cpu_bits.h                       |  1 +
>  target/riscv/csr.c                            | 13 +++-
>  .../riscv/insn_trans/trans_privileged.inc.c   |  2 +-
>  6 files changed, 71 insertions(+), 44 deletions(-)

Re: [Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions

[Alistair Francis]

On Wed, Jun 19, 2019 at 3:58 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote:
> > Based-on: <cover.1555726824.git.alistair.francis@wdc.com>
> >
> > Now that the RISC-V spec has started to be ratified let's update our
> > QEMU implementation. There are a few things going on here:
> >  - Add priv version 1.11.0 to QEMU
> >     - This is the ratified version of the Privledge spec
> >     - There are almost no changes to 1.10
> >  - Mark the 1.09.1 privledge spec as depreated
> >      - Let's aim to remove it in two releases
> >  - Set priv version 1.11.0 as the default
> >  - Remove the user_spec version
> >      - This doesn't really mean anything so let's remove it
> >  - Add support for the "Counters" extension
> >  - Add command line options for Zifencei and Zicsr
>
> Thanks!  I'll look at the code, but I've currently got this queued up behind
> your hypervisor patches so it might take a bit.  LMK if you want me to invert
> the priority on these.  I'll probably be buried until the start of July.

Let's move the Hypervisor patches to the back then. There is a new
spec version now anyway so I'll have to update them for that.

Alistair

>
> > We can remove the spec version as it's unused and has never been exposed
> > to users. The idea is to match the specs in specifying the version. To
> > handle versions in the future we can extend the extension props to
> > handle version information.
> >
> > For example something like this: -cpu rv64,i=2.2,c=2.0,h=0.4,priv_spec=1.11
> >
> > NOTE: This isn't supported today as we only have one of each version.
> >
> > This will be a future change if we decide to support multiple versions
> > of extensions.
> >
> > The "priv_spec" string doesn't really match, but I don't have a better
> > way to say "Machine ISA" and "Supervisor ISA" which is what is included
> > in "priv_spec".
> >
> > For completeness I have also added the Counters, Zifencei and Zicsr
> > extensions.
> >
> > Everything else seems to match the spec names/style.
> >
> > Please let me know if I'm missing something. QEMU 4.1 is the first
> > release to support the extensions from the command line, so we can
> > easily change it until then. After that it'll take more work to change
> > the command line interface.
> >
> > Alistair Francis (9):
> >   target/riscv: Restructure deprecatd CPUs
> >   target/riscv: Add the privledge spec version 1.11.0
> >   target/riscv: Comment in the mcountinhibit CSR
> >   target/riscv: Set privledge spec 1.11.0 as default
> >   qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1
> >   target/riscv: Require either I or E base extension
> >   target/riscv: Remove user version information
> >   target/riscv: Add support for disabling/enabling Counters
> >   target/riscv: Add Zifencei and Zicsr as command line options
> >
> >  qemu-deprecated.texi                          |  8 +++
> >  target/riscv/cpu.c                            | 72 ++++++++++---------
> >  target/riscv/cpu.h                            | 19 ++---
> >  target/riscv/cpu_bits.h                       |  1 +
> >  target/riscv/csr.c                            | 13 +++-
> >  .../riscv/insn_trans/trans_privileged.inc.c   |  2 +-
> >  6 files changed, 71 insertions(+), 44 deletions(-)

Re: [Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions

[Palmer Dabbelt]

On Wed, 19 Jun 2019 07:19:38 PDT (-0700), alistair23@gmail.com wrote:
> On Wed, Jun 19, 2019 at 3:58 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>>
>> On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote:
>> > Based-on: <cover.1555726824.git.alistair.francis@wdc.com>
>> >
>> > Now that the RISC-V spec has started to be ratified let's update our
>> > QEMU implementation. There are a few things going on here:
>> >  - Add priv version 1.11.0 to QEMU
>> >     - This is the ratified version of the Privledge spec
>> >     - There are almost no changes to 1.10
>> >  - Mark the 1.09.1 privledge spec as depreated
>> >      - Let's aim to remove it in two releases
>> >  - Set priv version 1.11.0 as the default
>> >  - Remove the user_spec version
>> >      - This doesn't really mean anything so let's remove it
>> >  - Add support for the "Counters" extension
>> >  - Add command line options for Zifencei and Zicsr
>>
>> Thanks!  I'll look at the code, but I've currently got this queued up behind
>> your hypervisor patches so it might take a bit.  LMK if you want me to invert
>> the priority on these.  I'll probably be buried until the start of July.
>
> Let's move the Hypervisor patches to the back then. There is a new
> spec version now anyway so I'll have to update them for that.

OK.  Do you want me to just drop them and wait for a v2 / draft 0.4?

>
> Alistair
>
>>
>> > We can remove the spec version as it's unused and has never been exposed
>> > to users. The idea is to match the specs in specifying the version. To
>> > handle versions in the future we can extend the extension props to
>> > handle version information.
>> >
>> > For example something like this: -cpu rv64,i=2.2,c=2.0,h=0.4,priv_spec=1.11
>> >
>> > NOTE: This isn't supported today as we only have one of each version.
>> >
>> > This will be a future change if we decide to support multiple versions
>> > of extensions.
>> >
>> > The "priv_spec" string doesn't really match, but I don't have a better
>> > way to say "Machine ISA" and "Supervisor ISA" which is what is included
>> > in "priv_spec".
>> >
>> > For completeness I have also added the Counters, Zifencei and Zicsr
>> > extensions.
>> >
>> > Everything else seems to match the spec names/style.
>> >
>> > Please let me know if I'm missing something. QEMU 4.1 is the first
>> > release to support the extensions from the command line, so we can
>> > easily change it until then. After that it'll take more work to change
>> > the command line interface.
>> >
>> > Alistair Francis (9):
>> >   target/riscv: Restructure deprecatd CPUs
>> >   target/riscv: Add the privledge spec version 1.11.0
>> >   target/riscv: Comment in the mcountinhibit CSR
>> >   target/riscv: Set privledge spec 1.11.0 as default
>> >   qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1
>> >   target/riscv: Require either I or E base extension
>> >   target/riscv: Remove user version information
>> >   target/riscv: Add support for disabling/enabling Counters
>> >   target/riscv: Add Zifencei and Zicsr as command line options
>> >
>> >  qemu-deprecated.texi                          |  8 +++
>> >  target/riscv/cpu.c                            | 72 ++++++++++---------
>> >  target/riscv/cpu.h                            | 19 ++---
>> >  target/riscv/cpu_bits.h                       |  1 +
>> >  target/riscv/csr.c                            | 13 +++-
>> >  .../riscv/insn_trans/trans_privileged.inc.c   |  2 +-
>> >  6 files changed, 71 insertions(+), 44 deletions(-)

Re: [Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions

[Alistair Francis]

On Thu, Jun 20, 2019 at 7:49 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Wed, 19 Jun 2019 07:19:38 PDT (-0700), alistair23@gmail.com wrote:
> > On Wed, Jun 19, 2019 at 3:58 AM Palmer Dabbelt <palmer@sifive.com> wrote:
> >>
> >> On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote:
> >> > Based-on: <cover.1555726824.git.alistair.francis@wdc.com>
> >> >
> >> > Now that the RISC-V spec has started to be ratified let's update our
> >> > QEMU implementation. There are a few things going on here:
> >> >  - Add priv version 1.11.0 to QEMU
> >> >     - This is the ratified version of the Privledge spec
> >> >     - There are almost no changes to 1.10
> >> >  - Mark the 1.09.1 privledge spec as depreated
> >> >      - Let's aim to remove it in two releases
> >> >  - Set priv version 1.11.0 as the default
> >> >  - Remove the user_spec version
> >> >      - This doesn't really mean anything so let's remove it
> >> >  - Add support for the "Counters" extension
> >> >  - Add command line options for Zifencei and Zicsr
> >>
> >> Thanks!  I'll look at the code, but I've currently got this queued up behind
> >> your hypervisor patches so it might take a bit.  LMK if you want me to invert
> >> the priority on these.  I'll probably be buried until the start of July.
> >
> > Let's move the Hypervisor patches to the back then. There is a new
> > spec version now anyway so I'll have to update them for that.
>
> OK.  Do you want me to just drop them and wait for a v2 / draft 0.4?

I haven't looked at the 0.4 yet, but I think there are still lots of
similarities so let's just put Hypervisor patches at the back of the
list and see if you get there. It would still be nice to have comments
on the v1.

Alistair

>
> >
> > Alistair
> >
> >>
> >> > We can remove the spec version as it's unused and has never been exposed
> >> > to users. The idea is to match the specs in specifying the version. To
> >> > handle versions in the future we can extend the extension props to
> >> > handle version information.
> >> >
> >> > For example something like this: -cpu rv64,i=2.2,c=2.0,h=0.4,priv_spec=1.11
> >> >
> >> > NOTE: This isn't supported today as we only have one of each version.
> >> >
> >> > This will be a future change if we decide to support multiple versions
> >> > of extensions.
> >> >
> >> > The "priv_spec" string doesn't really match, but I don't have a better
> >> > way to say "Machine ISA" and "Supervisor ISA" which is what is included
> >> > in "priv_spec".
> >> >
> >> > For completeness I have also added the Counters, Zifencei and Zicsr
> >> > extensions.
> >> >
> >> > Everything else seems to match the spec names/style.
> >> >
> >> > Please let me know if I'm missing something. QEMU 4.1 is the first
> >> > release to support the extensions from the command line, so we can
> >> > easily change it until then. After that it'll take more work to change
> >> > the command line interface.
> >> >
> >> > Alistair Francis (9):
> >> >   target/riscv: Restructure deprecatd CPUs
> >> >   target/riscv: Add the privledge spec version 1.11.0
> >> >   target/riscv: Comment in the mcountinhibit CSR
> >> >   target/riscv: Set privledge spec 1.11.0 as default
> >> >   qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1
> >> >   target/riscv: Require either I or E base extension
> >> >   target/riscv: Remove user version information
> >> >   target/riscv: Add support for disabling/enabling Counters
> >> >   target/riscv: Add Zifencei and Zicsr as command line options
> >> >
> >> >  qemu-deprecated.texi                          |  8 +++
> >> >  target/riscv/cpu.c                            | 72 ++++++++++---------
> >> >  target/riscv/cpu.h                            | 19 ++---
> >> >  target/riscv/cpu_bits.h                       |  1 +
> >> >  target/riscv/csr.c                            | 13 +++-
> >> >  .../riscv/insn_trans/trans_privileged.inc.c   |  2 +-
> >> >  6 files changed, 71 insertions(+), 44 deletions(-)

Re: [Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions

[Palmer Dabbelt]

On Fri, 21 Jun 2019 17:23:44 PDT (-0700), alistair23@gmail.com wrote:
> On Thu, Jun 20, 2019 at 7:49 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>>
>> On Wed, 19 Jun 2019 07:19:38 PDT (-0700), alistair23@gmail.com wrote:
>> > On Wed, Jun 19, 2019 at 3:58 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>> >>
>> >> On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote:
>> >> > Based-on: <cover.1555726824.git.alistair.francis@wdc.com>
>> >> >
>> >> > Now that the RISC-V spec has started to be ratified let's update our
>> >> > QEMU implementation. There are a few things going on here:
>> >> >  - Add priv version 1.11.0 to QEMU
>> >> >     - This is the ratified version of the Privledge spec
>> >> >     - There are almost no changes to 1.10
>> >> >  - Mark the 1.09.1 privledge spec as depreated
>> >> >      - Let's aim to remove it in two releases
>> >> >  - Set priv version 1.11.0 as the default
>> >> >  - Remove the user_spec version
>> >> >      - This doesn't really mean anything so let's remove it
>> >> >  - Add support for the "Counters" extension
>> >> >  - Add command line options for Zifencei and Zicsr
>> >>
>> >> Thanks!  I'll look at the code, but I've currently got this queued up behind
>> >> your hypervisor patches so it might take a bit.  LMK if you want me to invert
>> >> the priority on these.  I'll probably be buried until the start of July.
>> >
>> > Let's move the Hypervisor patches to the back then. There is a new
>> > spec version now anyway so I'll have to update them for that.
>>
>> OK.  Do you want me to just drop them and wait for a v2 / draft 0.4?
>
> I haven't looked at the 0.4 yet, but I think there are still lots of
> similarities so let's just put Hypervisor patches at the back of the
> list and see if you get there. It would still be nice to have comments
> on the v1.

Works for me.  I'm in Taiwan this week but I'm at the office, so with any luck
I'll have some time to actually work.

>
> Alistair
>
>>
>> >
>> > Alistair
>> >
>> >>
>> >> > We can remove the spec version as it's unused and has never been exposed
>> >> > to users. The idea is to match the specs in specifying the version. To
>> >> > handle versions in the future we can extend the extension props to
>> >> > handle version information.
>> >> >
>> >> > For example something like this: -cpu rv64,i=2.2,c=2.0,h=0.4,priv_spec=1.11
>> >> >
>> >> > NOTE: This isn't supported today as we only have one of each version.
>> >> >
>> >> > This will be a future change if we decide to support multiple versions
>> >> > of extensions.
>> >> >
>> >> > The "priv_spec" string doesn't really match, but I don't have a better
>> >> > way to say "Machine ISA" and "Supervisor ISA" which is what is included
>> >> > in "priv_spec".
>> >> >
>> >> > For completeness I have also added the Counters, Zifencei and Zicsr
>> >> > extensions.
>> >> >
>> >> > Everything else seems to match the spec names/style.
>> >> >
>> >> > Please let me know if I'm missing something. QEMU 4.1 is the first
>> >> > release to support the extensions from the command line, so we can
>> >> > easily change it until then. After that it'll take more work to change
>> >> > the command line interface.
>> >> >
>> >> > Alistair Francis (9):
>> >> >   target/riscv: Restructure deprecatd CPUs
>> >> >   target/riscv: Add the privledge spec version 1.11.0
>> >> >   target/riscv: Comment in the mcountinhibit CSR
>> >> >   target/riscv: Set privledge spec 1.11.0 as default
>> >> >   qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1
>> >> >   target/riscv: Require either I or E base extension
>> >> >   target/riscv: Remove user version information
>> >> >   target/riscv: Add support for disabling/enabling Counters
>> >> >   target/riscv: Add Zifencei and Zicsr as command line options
>> >> >
>> >> >  qemu-deprecated.texi                          |  8 +++
>> >> >  target/riscv/cpu.c                            | 72 ++++++++++---------
>> >> >  target/riscv/cpu.h                            | 19 ++---
>> >> >  target/riscv/cpu_bits.h                       |  1 +
>> >> >  target/riscv/csr.c                            | 13 +++-
>> >> >  .../riscv/insn_trans/trans_privileged.inc.c   |  2 +-
>> >> >  6 files changed, 71 insertions(+), 44 deletions(-)

Re: [Qemu-devel] [PATCH v1 3/9] target/riscv: Comment in the mcountinhibit CSR

[Palmer Dabbelt]

On Mon, 17 Jun 2019 18:31:08 PDT (-0700), Alistair Francis wrote:
> Add a comment for the new mcountinhibit which conflicts with the
> CSR_MUCOUNTEREN from version 1.09.1. This can be updated when we remove
> 1.09.1.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu_bits.h | 1 +
>  target/riscv/csr.c      | 6 ++++--
>  2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 47450a3cdb..11f971ad5d 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -136,6 +136,7 @@
>  #define CSR_MCOUNTEREN      0x306
>
>  /* Legacy Counter Setup (priv v1.9.1) */
> +/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
>  #define CSR_MUCOUNTEREN     0x320
>  #define CSR_MSCOUNTEREN     0x321
>  #define CSR_MHCOUNTEREN     0x322
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index c67d29e206..437387fd28 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -461,18 +461,20 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
>      return 0;
>  }
>
> +/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
>  static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
>  {
> -    if (env->priv_ver > PRIV_VERSION_1_09_1) {
> +    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
>          return -1;
>      }
>      *val = env->mcounteren;
>      return 0;
>  }
>
> +/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
>  static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
>  {
> -    if (env->priv_ver > PRIV_VERSION_1_09_1) {
> +    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
>          return -1;
>      }
>      env->mcounteren = val;

I don't think this one is right: this should be unsupported on 1.11, as the
semantics of this bit are slightly different.  It shouldn't be that hard to
just emulate it fully for both 1.09.1 and 1.11: for 1.09 this disables access
to the counters (which still tick), while for 1.11 it disables ticking the
counters (which can still be accessed).  Since we don't do anything with the
counters in QEMU, I think this should do it

LMK if you're OK with me replacing the patch with this

commit e9169ccd5ca97a036de41dad23f37f6724712b90
Author: Alistair Francis <alistair.francis@wdc.com>
Date:   Mon Jun 17 18:31:08 2019 -0700

    target/riscv: Add the mcountinhibit CSR

    1.11 defines mcountinhibit, which has the same numeric CSR value as
    mucounteren from 1.09.1 but has different semantics.  This patch enables
    the CSR for 1.11-based targets, which is trivial to implement because
    the counters in QEMU never tick (legal according to the spec).

    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
    [Palmer: Fix counter access semantics, change commit message to indicate
    the behavior is fully emulated.]
    Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
    Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 47450a3cdb75..11f971ad5df0 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -136,6 +136,7 @@
 #define CSR_MCOUNTEREN      0x306

 /* Legacy Counter Setup (priv v1.9.1) */
+/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
 #define CSR_MUCOUNTEREN     0x320
 #define CSR_MSCOUNTEREN     0x321
 #define CSR_MHCOUNTEREN     0x322
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c67d29e20618..2622b2e05474 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -56,6 +56,14 @@ static int fs(CPURISCVState *env, int csrno)
 static int ctr(CPURISCVState *env, int csrno)
 {
 #if !defined(CONFIG_USER_ONLY)
+    /*
+     * The counters are always enabled on newer priv specs, as the CSR has
+     * changed from controlling that the counters can be read to controlling
+     * that the counters increment.
+     */
+    if (env->priv_ver > PRIV_VERSION_1_09_1)
+        return 0;
+
     uint32_t ctr_en = ~0u;

     if (env->priv < PRV_M) {
@@ -461,18 +469,20 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }

+/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
 {
-    if (env->priv_ver > PRIV_VERSION_1_09_1) {
+    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
         return -1;
     }
     *val = env->mcounteren;
     return 0;
 }

+/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
 {
-    if (env->priv_ver > PRIV_VERSION_1_09_1) {
+    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
         return -1;
     }
     env->mcounteren = val;

Re: [Qemu-devel] [PATCH v1 9/9] target/riscv: Add Zifencei and Zicsr as command line options

[Palmer Dabbelt]

On Mon, 17 Jun 2019 18:31:25 PDT (-0700), Alistair Francis wrote:
> For completeness let's add Zifencei and Zicsr as command line options,
> even though they can't be disabled at the moment.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu.c | 9 +++++++++
>  target/riscv/cpu.h | 2 ++
>  2 files changed, 11 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 5af1c9b38c..53cf8607f7 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -409,6 +409,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>          set_misa(env, RVXLEN | target_misa);
>      }
>
> +    if (!cpu->cfg.ext_ifencei) {
> +        warn_report("QEMU does not support disabling Zifencei");
> +    }
> +    if (!cpu->cfg.ext_icsr) {
> +        warn_report("QEMU does not support disabling Zicsr");
> +    }
> +
>      riscv_cpu_register_gdb_regs_for_features(cs);
>
>      qemu_init_vcpu(cs);
> @@ -441,6 +448,8 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> +    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> +    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>      DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
>      DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>      DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 786f620564..b4c212dfcf 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -222,6 +222,8 @@ typedef struct RISCVCPU {
>          bool ext_s;
>          bool ext_u;
>          bool ext_counters;
> +        bool ext_ifencei;
> +        bool ext_icsr;
>
>          char *priv_spec;
>          char *user_spec;

I'd rather just support these, which seems about as hard as emitting a warning.
Disabling Zifencei is particularly useful, as the Linux ABI forbids it so this
way we can run tests that way.  Unless I'm missing something, I think these two
should do it:

From 6d645eb1e8ba4d16431af40bf04e5c165475bf5a Mon Sep 17 00:00:00 2001
From: Palmer Dabbelt <palmer@sifive.com>
Date: Mon, 24 Jun 2019 01:59:05 -0700
Subject: [PATCH 1/2] RISC-V: Add support for the Zifencei extension

fence.i has been split out of the base ISA as part of the ratification
process.  This patch adds a Zifencei argument, which disables the
fence.i instruction.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/cpu.c                      | 1 +
 target/riscv/cpu.h                      | 1 +
 target/riscv/insn_trans/trans_rvi.inc.c | 3 +++
 target/riscv/translate.c                | 3 +++
 4 files changed, 8 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index be90fa7d0808..bbad39a337b3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -441,6 +441,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4d4e0f89e206..ba551cd3082c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -223,6 +223,7 @@ typedef struct RISCVCPU {
         bool ext_s;
         bool ext_u;
         bool ext_counters;
+        bool ext_ifencei;
 
         char *priv_spec;
         char *user_spec;
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 6cda078ed6ba..766594ba08ce 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -484,6 +484,9 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a)
 
 static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
 {
+    if (!ctx->ext_ifencei)
+        return false;
+
     /*
      * FENCE_I is a no-op in QEMU,
      * however we need to end the translation block
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 313c27b70073..8d6ab732588d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -54,6 +54,7 @@ typedef struct DisasContext {
        to any system register, which includes CSR_FRM, so we do not have
        to reset this known value.  */
     int frm;
+    bool ext_ifencei;
 } DisasContext;
 
 #ifdef TARGET_RISCV64
@@ -752,6 +753,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
     CPURISCVState *env = cs->env_ptr;
+    RISCVCPU *cpu = RISCV_CPU(cs);
 
     ctx->pc_succ_insn = ctx->base.pc_first;
     ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
@@ -759,6 +761,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->priv_ver = env->priv_ver;
     ctx->misa = env->misa;
     ctx->frm = -1;  /* unknown rounding mode */
+    ctx->ext_ifencei = cpu->cfg.ext_ifencei;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.21.0


From 6d280048f076eb0f28ee0c4454a1ed8b130240cb Mon Sep 17 00:00:00 2001
From: Palmer Dabbelt <palmer@sifive.com>
Date: Mon, 24 Jun 2019 01:59:51 -0700
Subject: [PATCH 2/2] RISC-V: Add support for the Zicsr extension

The various CSR instructions have been split out of the base ISA as part
of the ratification process.  This patch adds a Zicsr argument, which
disables all the CSR instructions.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/cpu.c                      |  1 +
 target/riscv/cpu.h                      |  1 +
 target/riscv/insn_trans/trans_rvi.inc.c | 18 ++++++++++++++++++
 target/riscv/translate.c                |  2 ++
 4 files changed, 22 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bbad39a337b3..915b9e77df33 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -442,6 +442,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ba551cd3082c..0adb307f3298 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -224,6 +224,7 @@ typedef struct RISCVCPU {
         bool ext_u;
         bool ext_counters;
         bool ext_ifencei;
+        bool ext_icsr;
 
         char *priv_spec;
         char *user_spec;
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 766594ba08ce..66c5202cc5d6 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -524,6 +524,9 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
 
 static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
 {
+    if (!ctx->ext_icsr)
+        return false;
+
     TCGv source1, csr_store, dest, rs1_pass;
     RISCV_OP_CSR_PRE;
     gen_helper_csrrw(dest, cpu_env, source1, csr_store);
@@ -533,6 +536,9 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
 
 static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
 {
+    if (!ctx->ext_icsr)
+        return false;
+
     TCGv source1, csr_store, dest, rs1_pass;
     RISCV_OP_CSR_PRE;
     gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
@@ -542,6 +548,9 @@ static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
 
 static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
 {
+    if (!ctx->ext_icsr)
+        return false;
+
     TCGv source1, csr_store, dest, rs1_pass;
     RISCV_OP_CSR_PRE;
     gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
@@ -551,6 +560,9 @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
 
 static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
 {
+    if (!ctx->ext_icsr)
+        return false;
+
     TCGv source1, csr_store, dest, rs1_pass;
     RISCV_OP_CSR_PRE;
     gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
@@ -560,6 +572,9 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
 
 static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
 {
+    if (!ctx->ext_icsr)
+        return false;
+
     TCGv source1, csr_store, dest, rs1_pass;
     RISCV_OP_CSR_PRE;
     gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
@@ -569,6 +584,9 @@ static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
 
 static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
 {
+    if (!ctx->ext_icsr)
+        return false;
+
     TCGv source1, csr_store, dest, rs1_pass;
     RISCV_OP_CSR_PRE;
     gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8d6ab732588d..be46435b9a7b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -55,6 +55,7 @@ typedef struct DisasContext {
        to reset this known value.  */
     int frm;
     bool ext_ifencei;
+    bool ext_icsr;
 } DisasContext;
 
 #ifdef TARGET_RISCV64
@@ -762,6 +763,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->misa = env->misa;
     ctx->frm = -1;  /* unknown rounding mode */
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
+    ctx->ext_icsr = cpu->cfg.ext_icsr;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.21.0

Re: [Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions

[Palmer Dabbelt]

On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote:
> Based-on: <cover.1555726824.git.alistair.francis@wdc.com>
>
> Now that the RISC-V spec has started to be ratified let's update our
> QEMU implementation. There are a few things going on here:
>  - Add priv version 1.11.0 to QEMU
>     - This is the ratified version of the Privledge spec
>     - There are almost no changes to 1.10
>  - Mark the 1.09.1 privledge spec as depreated
>      - Let's aim to remove it in two releases
>  - Set priv version 1.11.0 as the default
>  - Remove the user_spec version
>      - This doesn't really mean anything so let's remove it
>  - Add support for the "Counters" extension
>  - Add command line options for Zifencei and Zicsr
>
> We can remove the spec version as it's unused and has never been exposed
> to users. The idea is to match the specs in specifying the version. To
> handle versions in the future we can extend the extension props to
> handle version information.
>
> For example something like this: -cpu rv64,i=2.2,c=2.0,h=0.4,priv_spec=1.11
>
> NOTE: This isn't supported today as we only have one of each version.
>
> This will be a future change if we decide to support multiple versions
> of extensions.
>
> The "priv_spec" string doesn't really match, but I don't have a better
> way to say "Machine ISA" and "Supervisor ISA" which is what is included
> in "priv_spec".
>
> For completeness I have also added the Counters, Zifencei and Zicsr
> extensions.
>
> Everything else seems to match the spec names/style.
>
> Please let me know if I'm missing something. QEMU 4.1 is the first
> release to support the extensions from the command line, so we can
> easily change it until then. After that it'll take more work to change
> the command line interface.
>
> Alistair Francis (9):
>   target/riscv: Restructure deprecatd CPUs
>   target/riscv: Add the privledge spec version 1.11.0
>   target/riscv: Comment in the mcountinhibit CSR
>   target/riscv: Set privledge spec 1.11.0 as default
>   qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1
>   target/riscv: Require either I or E base extension
>   target/riscv: Remove user version information
>   target/riscv: Add support for disabling/enabling Counters
>   target/riscv: Add Zifencei and Zicsr as command line options
>
>  qemu-deprecated.texi                          |  8 +++
>  target/riscv/cpu.c                            | 72 ++++++++++---------
>  target/riscv/cpu.h                            | 19 ++---
>  target/riscv/cpu_bits.h                       |  1 +
>  target/riscv/csr.c                            | 13 +++-
>  .../riscv/insn_trans/trans_privileged.inc.c   |  2 +-
>  6 files changed, 71 insertions(+), 44 deletions(-)

Aside from the comments on 3 and 9

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

I've got these, along with my proposed modifications, queued up.  LMK if that's
a problem, particularly the two-patch replacement for 9 needs a review as it's
entirely new code.

Re: [Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions

[Alistair Francis]

On Mon, Jun 24, 2019 at 2:33 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote:
> > Based-on: <cover.1555726824.git.alistair.francis@wdc.com>
> >
> > Now that the RISC-V spec has started to be ratified let's update our
> > QEMU implementation. There are a few things going on here:
> >  - Add priv version 1.11.0 to QEMU
> >     - This is the ratified version of the Privledge spec
> >     - There are almost no changes to 1.10
> >  - Mark the 1.09.1 privledge spec as depreated
> >      - Let's aim to remove it in two releases
> >  - Set priv version 1.11.0 as the default
> >  - Remove the user_spec version
> >      - This doesn't really mean anything so let's remove it
> >  - Add support for the "Counters" extension
> >  - Add command line options for Zifencei and Zicsr
> >
> > We can remove the spec version as it's unused and has never been exposed
> > to users. The idea is to match the specs in specifying the version. To
> > handle versions in the future we can extend the extension props to
> > handle version information.
> >
> > For example something like this: -cpu rv64,i=2.2,c=2.0,h=0.4,priv_spec=1.11
> >
> > NOTE: This isn't supported today as we only have one of each version.
> >
> > This will be a future change if we decide to support multiple versions
> > of extensions.
> >
> > The "priv_spec" string doesn't really match, but I don't have a better
> > way to say "Machine ISA" and "Supervisor ISA" which is what is included
> > in "priv_spec".
> >
> > For completeness I have also added the Counters, Zifencei and Zicsr
> > extensions.
> >
> > Everything else seems to match the spec names/style.
> >
> > Please let me know if I'm missing something. QEMU 4.1 is the first
> > release to support the extensions from the command line, so we can
> > easily change it until then. After that it'll take more work to change
> > the command line interface.
> >
> > Alistair Francis (9):
> >   target/riscv: Restructure deprecatd CPUs
> >   target/riscv: Add the privledge spec version 1.11.0
> >   target/riscv: Comment in the mcountinhibit CSR
> >   target/riscv: Set privledge spec 1.11.0 as default
> >   qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1
> >   target/riscv: Require either I or E base extension
> >   target/riscv: Remove user version information
> >   target/riscv: Add support for disabling/enabling Counters
> >   target/riscv: Add Zifencei and Zicsr as command line options
> >
> >  qemu-deprecated.texi                          |  8 +++
> >  target/riscv/cpu.c                            | 72 ++++++++++---------
> >  target/riscv/cpu.h                            | 19 ++---
> >  target/riscv/cpu_bits.h                       |  1 +
> >  target/riscv/csr.c                            | 13 +++-
> >  .../riscv/insn_trans/trans_privileged.inc.c   |  2 +-
> >  6 files changed, 71 insertions(+), 44 deletions(-)
>
> Aside from the comments on 3 and 9
>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>
> I've got these, along with my proposed modifications, queued up.  LMK if that's
> a problem, particularly the two-patch replacement for 9 needs a review as it's
> entirely new code.

I haven't looked at the new code yet, but it all passes my tests so LGTM.

Alistair

Re: [Qemu-devel] [PATCH v1 3/9] target/riscv: Comment in the mcountinhibit CSR

[Alistair Francis]

On Mon, Jun 24, 2019 at 2:31 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Mon, 17 Jun 2019 18:31:08 PDT (-0700), Alistair Francis wrote:
> > Add a comment for the new mcountinhibit which conflicts with the
> > CSR_MUCOUNTEREN from version 1.09.1. This can be updated when we remove
> > 1.09.1.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >  target/riscv/cpu_bits.h | 1 +
> >  target/riscv/csr.c      | 6 ++++--
> >  2 files changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index 47450a3cdb..11f971ad5d 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -136,6 +136,7 @@
> >  #define CSR_MCOUNTEREN      0x306
> >
> >  /* Legacy Counter Setup (priv v1.9.1) */
> > +/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
> >  #define CSR_MUCOUNTEREN     0x320
> >  #define CSR_MSCOUNTEREN     0x321
> >  #define CSR_MHCOUNTEREN     0x322
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index c67d29e206..437387fd28 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -461,18 +461,20 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
> >      return 0;
> >  }
> >
> > +/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
> >  static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
> >  {
> > -    if (env->priv_ver > PRIV_VERSION_1_09_1) {
> > +    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
> >          return -1;
> >      }
> >      *val = env->mcounteren;
> >      return 0;
> >  }
> >
> > +/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
> >  static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
> >  {
> > -    if (env->priv_ver > PRIV_VERSION_1_09_1) {
> > +    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
> >          return -1;
> >      }
> >      env->mcounteren = val;
>
> I don't think this one is right: this should be unsupported on 1.11, as the
> semantics of this bit are slightly different.  It shouldn't be that hard to
> just emulate it fully for both 1.09.1 and 1.11: for 1.09 this disables access
> to the counters (which still tick), while for 1.11 it disables ticking the
> counters (which can still be accessed).  Since we don't do anything with the
> counters in QEMU, I think this should do it
>
> LMK if you're OK with me replacing the patch with this
>
> commit e9169ccd5ca97a036de41dad23f37f6724712b90
> Author: Alistair Francis <alistair.francis@wdc.com>
> Date:   Mon Jun 17 18:31:08 2019 -0700
>
>     target/riscv: Add the mcountinhibit CSR
>
>     1.11 defines mcountinhibit, which has the same numeric CSR value as
>     mucounteren from 1.09.1 but has different semantics.  This patch enables
>     the CSR for 1.11-based targets, which is trivial to implement because
>     the counters in QEMU never tick (legal according to the spec).
>
>     Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>     [Palmer: Fix counter access semantics, change commit message to indicate
>     the behavior is fully emulated.]
>     Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>     Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

Yep, looks good.

Alistair

>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 47450a3cdb75..11f971ad5df0 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -136,6 +136,7 @@
>  #define CSR_MCOUNTEREN      0x306
>
>  /* Legacy Counter Setup (priv v1.9.1) */
> +/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
>  #define CSR_MUCOUNTEREN     0x320
>  #define CSR_MSCOUNTEREN     0x321
>  #define CSR_MHCOUNTEREN     0x322
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index c67d29e20618..2622b2e05474 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -56,6 +56,14 @@ static int fs(CPURISCVState *env, int csrno)
>  static int ctr(CPURISCVState *env, int csrno)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> +    /*
> +     * The counters are always enabled on newer priv specs, as the CSR has
> +     * changed from controlling that the counters can be read to controlling
> +     * that the counters increment.
> +     */
> +    if (env->priv_ver > PRIV_VERSION_1_09_1)
> +        return 0;
> +
>      uint32_t ctr_en = ~0u;
>
>      if (env->priv < PRV_M) {
> @@ -461,18 +469,20 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
>      return 0;
>  }
>
> +/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
>  static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
>  {
> -    if (env->priv_ver > PRIV_VERSION_1_09_1) {
> +    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
>          return -1;
>      }
>      *val = env->mcounteren;
>      return 0;
>  }
>
> +/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
>  static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
>  {
> -    if (env->priv_ver > PRIV_VERSION_1_09_1) {
> +    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
>          return -1;
>      }
>      env->mcounteren = val;

Re: [Qemu-devel] [PATCH v1 9/9] target/riscv: Add Zifencei and Zicsr as command line options

[Alistair Francis]

On Mon, Jun 24, 2019 at 2:31 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Mon, 17 Jun 2019 18:31:25 PDT (-0700), Alistair Francis wrote:
> > For completeness let's add Zifencei and Zicsr as command line options,
> > even though they can't be disabled at the moment.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >  target/riscv/cpu.c | 9 +++++++++
> >  target/riscv/cpu.h | 2 ++
> >  2 files changed, 11 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 5af1c9b38c..53cf8607f7 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -409,6 +409,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> >          set_misa(env, RVXLEN | target_misa);
> >      }
> >
> > +    if (!cpu->cfg.ext_ifencei) {
> > +        warn_report("QEMU does not support disabling Zifencei");
> > +    }
> > +    if (!cpu->cfg.ext_icsr) {
> > +        warn_report("QEMU does not support disabling Zicsr");
> > +    }
> > +
> >      riscv_cpu_register_gdb_regs_for_features(cs);
> >
> >      qemu_init_vcpu(cs);
> > @@ -441,6 +448,8 @@ static Property riscv_cpu_properties[] = {
> >      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
> >      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
> >      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> > +    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> > +    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> >      DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> >      DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> >      DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 786f620564..b4c212dfcf 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -222,6 +222,8 @@ typedef struct RISCVCPU {
> >          bool ext_s;
> >          bool ext_u;
> >          bool ext_counters;
> > +        bool ext_ifencei;
> > +        bool ext_icsr;
> >
> >          char *priv_spec;
> >          char *user_spec;
>
> I'd rather just support these, which seems about as hard as emitting a warning.
> Disabling Zifencei is particularly useful, as the Linux ABI forbids it so this
> way we can run tests that way.  Unless I'm missing something, I think these two
> should do it:
>
> From 6d645eb1e8ba4d16431af40bf04e5c165475bf5a Mon Sep 17 00:00:00 2001
> From: Palmer Dabbelt <palmer@sifive.com>
> Date: Mon, 24 Jun 2019 01:59:05 -0700
> Subject: [PATCH 1/2] RISC-V: Add support for the Zifencei extension
>
> fence.i has been split out of the base ISA as part of the ratification
> process.  This patch adds a Zifencei argument, which disables the
> fence.i instruction.
>
> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

This looks good.

> ---
>  target/riscv/cpu.c                      | 1 +
>  target/riscv/cpu.h                      | 1 +
>  target/riscv/insn_trans/trans_rvi.inc.c | 3 +++
>  target/riscv/translate.c                | 3 +++
>  4 files changed, 8 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index be90fa7d0808..bbad39a337b3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -441,6 +441,7 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> +    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
>      DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
>      DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>      DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 4d4e0f89e206..ba551cd3082c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -223,6 +223,7 @@ typedef struct RISCVCPU {
>          bool ext_s;
>          bool ext_u;
>          bool ext_counters;
> +        bool ext_ifencei;
>
>          char *priv_spec;
>          char *user_spec;
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index 6cda078ed6ba..766594ba08ce 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -484,6 +484,9 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a)
>
>  static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
>  {
> +    if (!ctx->ext_ifencei)
> +        return false;
> +
>      /*
>       * FENCE_I is a no-op in QEMU,
>       * however we need to end the translation block
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 313c27b70073..8d6ab732588d 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -54,6 +54,7 @@ typedef struct DisasContext {
>         to any system register, which includes CSR_FRM, so we do not have
>         to reset this known value.  */
>      int frm;
> +    bool ext_ifencei;
>  } DisasContext;
>
>  #ifdef TARGET_RISCV64
> @@ -752,6 +753,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>  {
>      DisasContext *ctx = container_of(dcbase, DisasContext, base);
>      CPURISCVState *env = cs->env_ptr;
> +    RISCVCPU *cpu = RISCV_CPU(cs);
>
>      ctx->pc_succ_insn = ctx->base.pc_first;
>      ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
> @@ -759,6 +761,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>      ctx->priv_ver = env->priv_ver;
>      ctx->misa = env->misa;
>      ctx->frm = -1;  /* unknown rounding mode */
> +    ctx->ext_ifencei = cpu->cfg.ext_ifencei;
>  }
>
>  static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
> --
> 2.21.0
>
>
> From 6d280048f076eb0f28ee0c4454a1ed8b130240cb Mon Sep 17 00:00:00 2001
> From: Palmer Dabbelt <palmer@sifive.com>
> Date: Mon, 24 Jun 2019 01:59:51 -0700
> Subject: [PATCH 2/2] RISC-V: Add support for the Zicsr extension
>
> The various CSR instructions have been split out of the base ISA as part
> of the ratification process.  This patch adds a Zicsr argument, which
> disables all the CSR instructions.
>
> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

Couldn't we just do this in riscv_csrrw() to avoid passing it down to
the translation?

It gets called by all of these functions anyway.

Alistair

> ---
>  target/riscv/cpu.c                      |  1 +
>  target/riscv/cpu.h                      |  1 +
>  target/riscv/insn_trans/trans_rvi.inc.c | 18 ++++++++++++++++++
>  target/riscv/translate.c                |  2 ++
>  4 files changed, 22 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index bbad39a337b3..915b9e77df33 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -442,6 +442,7 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
>      DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> +    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>      DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
>      DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>      DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index ba551cd3082c..0adb307f3298 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -224,6 +224,7 @@ typedef struct RISCVCPU {
>          bool ext_u;
>          bool ext_counters;
>          bool ext_ifencei;
> +        bool ext_icsr;
>
>          char *priv_spec;
>          char *user_spec;
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index 766594ba08ce..66c5202cc5d6 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -524,6 +524,9 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
>
>  static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
>  {
> +    if (!ctx->ext_icsr)
> +        return false;
> +
>      TCGv source1, csr_store, dest, rs1_pass;
>      RISCV_OP_CSR_PRE;
>      gen_helper_csrrw(dest, cpu_env, source1, csr_store);
> @@ -533,6 +536,9 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
>
>  static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
>  {
> +    if (!ctx->ext_icsr)
> +        return false;
> +
>      TCGv source1, csr_store, dest, rs1_pass;
>      RISCV_OP_CSR_PRE;
>      gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
> @@ -542,6 +548,9 @@ static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
>
>  static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
>  {
> +    if (!ctx->ext_icsr)
> +        return false;
> +
>      TCGv source1, csr_store, dest, rs1_pass;
>      RISCV_OP_CSR_PRE;
>      gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
> @@ -551,6 +560,9 @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
>
>  static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
>  {
> +    if (!ctx->ext_icsr)
> +        return false;
> +
>      TCGv source1, csr_store, dest, rs1_pass;
>      RISCV_OP_CSR_PRE;
>      gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
> @@ -560,6 +572,9 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
>
>  static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
>  {
> +    if (!ctx->ext_icsr)
> +        return false;
> +
>      TCGv source1, csr_store, dest, rs1_pass;
>      RISCV_OP_CSR_PRE;
>      gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
> @@ -569,6 +584,9 @@ static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
>
>  static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
>  {
> +    if (!ctx->ext_icsr)
> +        return false;
> +
>      TCGv source1, csr_store, dest, rs1_pass;
>      RISCV_OP_CSR_PRE;
>      gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 8d6ab732588d..be46435b9a7b 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -55,6 +55,7 @@ typedef struct DisasContext {
>         to reset this known value.  */
>      int frm;
>      bool ext_ifencei;
> +    bool ext_icsr;
>  } DisasContext;
>
>  #ifdef TARGET_RISCV64
> @@ -762,6 +763,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>      ctx->misa = env->misa;
>      ctx->frm = -1;  /* unknown rounding mode */
>      ctx->ext_ifencei = cpu->cfg.ext_ifencei;
> +    ctx->ext_icsr = cpu->cfg.ext_icsr;
>  }
>
>  static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
> --
> 2.21.0
>

Re: [Qemu-devel] [PATCH v1 9/9] target/riscv: Add Zifencei and Zicsr as command line options

[Palmer Dabbelt]

On Mon, 24 Jun 2019 16:16:30 PDT (-0700), alistair23@gmail.com wrote:
> On Mon, Jun 24, 2019 at 2:31 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>>
>> On Mon, 17 Jun 2019 18:31:25 PDT (-0700), Alistair Francis wrote:
>> > For completeness let's add Zifencei and Zicsr as command line options,
>> > even though they can't be disabled at the moment.
>> >
>> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> > ---
>> >  target/riscv/cpu.c | 9 +++++++++
>> >  target/riscv/cpu.h | 2 ++
>> >  2 files changed, 11 insertions(+)
>> >
>> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> > index 5af1c9b38c..53cf8607f7 100644
>> > --- a/target/riscv/cpu.c
>> > +++ b/target/riscv/cpu.c
>> > @@ -409,6 +409,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> >          set_misa(env, RVXLEN | target_misa);
>> >      }
>> >
>> > +    if (!cpu->cfg.ext_ifencei) {
>> > +        warn_report("QEMU does not support disabling Zifencei");
>> > +    }
>> > +    if (!cpu->cfg.ext_icsr) {
>> > +        warn_report("QEMU does not support disabling Zicsr");
>> > +    }
>> > +
>> >      riscv_cpu_register_gdb_regs_for_features(cs);
>> >
>> >      qemu_init_vcpu(cs);
>> > @@ -441,6 +448,8 @@ static Property riscv_cpu_properties[] = {
>> >      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>> >      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>> >      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
>> > +    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
>> > +    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>> >      DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
>> >      DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>> >      DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
>> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> > index 786f620564..b4c212dfcf 100644
>> > --- a/target/riscv/cpu.h
>> > +++ b/target/riscv/cpu.h
>> > @@ -222,6 +222,8 @@ typedef struct RISCVCPU {
>> >          bool ext_s;
>> >          bool ext_u;
>> >          bool ext_counters;
>> > +        bool ext_ifencei;
>> > +        bool ext_icsr;
>> >
>> >          char *priv_spec;
>> >          char *user_spec;
>>
>> I'd rather just support these, which seems about as hard as emitting a warning.
>> Disabling Zifencei is particularly useful, as the Linux ABI forbids it so this
>> way we can run tests that way.  Unless I'm missing something, I think these two
>> should do it:
>>
>> From 6d645eb1e8ba4d16431af40bf04e5c165475bf5a Mon Sep 17 00:00:00 2001
>> From: Palmer Dabbelt <palmer@sifive.com>
>> Date: Mon, 24 Jun 2019 01:59:05 -0700
>> Subject: [PATCH 1/2] RISC-V: Add support for the Zifencei extension
>>
>> fence.i has been split out of the base ISA as part of the ratification
>> process.  This patch adds a Zifencei argument, which disables the
>> fence.i instruction.
>>
>> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
>
> This looks good.
>
>> ---
>>  target/riscv/cpu.c                      | 1 +
>>  target/riscv/cpu.h                      | 1 +
>>  target/riscv/insn_trans/trans_rvi.inc.c | 3 +++
>>  target/riscv/translate.c                | 3 +++
>>  4 files changed, 8 insertions(+)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index be90fa7d0808..bbad39a337b3 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -441,6 +441,7 @@ static Property riscv_cpu_properties[] = {
>>      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>>      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>>      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
>> +    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
>>      DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
>>      DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>>      DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 4d4e0f89e206..ba551cd3082c 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -223,6 +223,7 @@ typedef struct RISCVCPU {
>>          bool ext_s;
>>          bool ext_u;
>>          bool ext_counters;
>> +        bool ext_ifencei;
>>
>>          char *priv_spec;
>>          char *user_spec;
>> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
>> index 6cda078ed6ba..766594ba08ce 100644
>> --- a/target/riscv/insn_trans/trans_rvi.inc.c
>> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
>> @@ -484,6 +484,9 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a)
>>
>>  static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
>>  {
>> +    if (!ctx->ext_ifencei)
>> +        return false;
>> +
>>      /*
>>       * FENCE_I is a no-op in QEMU,
>>       * however we need to end the translation block
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index 313c27b70073..8d6ab732588d 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -54,6 +54,7 @@ typedef struct DisasContext {
>>         to any system register, which includes CSR_FRM, so we do not have
>>         to reset this known value.  */
>>      int frm;
>> +    bool ext_ifencei;
>>  } DisasContext;
>>
>>  #ifdef TARGET_RISCV64
>> @@ -752,6 +753,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>>  {
>>      DisasContext *ctx = container_of(dcbase, DisasContext, base);
>>      CPURISCVState *env = cs->env_ptr;
>> +    RISCVCPU *cpu = RISCV_CPU(cs);
>>
>>      ctx->pc_succ_insn = ctx->base.pc_first;
>>      ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
>> @@ -759,6 +761,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>>      ctx->priv_ver = env->priv_ver;
>>      ctx->misa = env->misa;
>>      ctx->frm = -1;  /* unknown rounding mode */
>> +    ctx->ext_ifencei = cpu->cfg.ext_ifencei;
>>  }
>>
>>  static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
>> --
>> 2.21.0
>>
>>
>> From 6d280048f076eb0f28ee0c4454a1ed8b130240cb Mon Sep 17 00:00:00 2001
>> From: Palmer Dabbelt <palmer@sifive.com>
>> Date: Mon, 24 Jun 2019 01:59:51 -0700
>> Subject: [PATCH 2/2] RISC-V: Add support for the Zicsr extension
>>
>> The various CSR instructions have been split out of the base ISA as part
>> of the ratification process.  This patch adds a Zicsr argument, which
>> disables all the CSR instructions.
>>
>> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
>
> Couldn't we just do this in riscv_csrrw() to avoid passing it down to
> the translation?
>
> It gets called by all of these functions anyway.

Ya, that's much cleaner.

$ git show bc9e214eff71c6a5467e8311701de49d009069e9 | cat
commit bc9e214eff71c6a5467e8311701de49d009069e9
gpg: Signature made Tue 25 Jun 2019 02:59:24 AM PDT
gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
gpg:                issuer "palmer@dabbelt.com"
gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [ultimate]
gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [ultimate]
Author: Palmer Dabbelt <palmer@sifive.com>
Date:   Mon Jun 24 01:59:51 2019 -0700

    RISC-V: Add support for the Zicsr extension

    The various CSR instructions have been split out of the base ISA as part
    of the ratification process.  This patch adds a Zicsr argument, which
    disables all the CSR instructions.

    Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bbad39a337b3..915b9e77df33 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -442,6 +442,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ba551cd3082c..0adb307f3298 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -224,6 +224,7 @@ typedef struct RISCVCPU {
         bool ext_u;
         bool ext_counters;
         bool ext_ifencei;
+        bool ext_icsr;

         char *priv_spec;
         char *user_spec;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index dad9ae4a147d..a2ae64bda42b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -790,6 +790,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 {
     int ret;
     target_ulong old_value;
+    RISCVCPU *cpu = env_archcpu(env);

     /* check privileges and return -1 if check fails */
 #if !defined(CONFIG_USER_ONLY)
@@ -800,6 +801,10 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
     }
 #endif

+    /* ensure the CSR extension is enabled. */
+    if (!cpu->cfg.ext_icsr)
+        return -1;
+
     /* check predicate */
     if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
         return -1;

>
> Alistair
>
>> ---
>>  target/riscv/cpu.c                      |  1 +
>>  target/riscv/cpu.h                      |  1 +
>>  target/riscv/insn_trans/trans_rvi.inc.c | 18 ++++++++++++++++++
>>  target/riscv/translate.c                |  2 ++
>>  4 files changed, 22 insertions(+)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index bbad39a337b3..915b9e77df33 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -442,6 +442,7 @@ static Property riscv_cpu_properties[] = {
>>      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>>      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
>>      DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
>> +    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>>      DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
>>      DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>>      DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index ba551cd3082c..0adb307f3298 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -224,6 +224,7 @@ typedef struct RISCVCPU {
>>          bool ext_u;
>>          bool ext_counters;
>>          bool ext_ifencei;
>> +        bool ext_icsr;
>>
>>          char *priv_spec;
>>          char *user_spec;
>> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
>> index 766594ba08ce..66c5202cc5d6 100644
>> --- a/target/riscv/insn_trans/trans_rvi.inc.c
>> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
>> @@ -524,6 +524,9 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
>>
>>  static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
>>  {
>> +    if (!ctx->ext_icsr)
>> +        return false;
>> +
>>      TCGv source1, csr_store, dest, rs1_pass;
>>      RISCV_OP_CSR_PRE;
>>      gen_helper_csrrw(dest, cpu_env, source1, csr_store);
>> @@ -533,6 +536,9 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
>>
>>  static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
>>  {
>> +    if (!ctx->ext_icsr)
>> +        return false;
>> +
>>      TCGv source1, csr_store, dest, rs1_pass;
>>      RISCV_OP_CSR_PRE;
>>      gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
>> @@ -542,6 +548,9 @@ static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
>>
>>  static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
>>  {
>> +    if (!ctx->ext_icsr)
>> +        return false;
>> +
>>      TCGv source1, csr_store, dest, rs1_pass;
>>      RISCV_OP_CSR_PRE;
>>      gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
>> @@ -551,6 +560,9 @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
>>
>>  static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
>>  {
>> +    if (!ctx->ext_icsr)
>> +        return false;
>> +
>>      TCGv source1, csr_store, dest, rs1_pass;
>>      RISCV_OP_CSR_PRE;
>>      gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
>> @@ -560,6 +572,9 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
>>
>>  static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
>>  {
>> +    if (!ctx->ext_icsr)
>> +        return false;
>> +
>>      TCGv source1, csr_store, dest, rs1_pass;
>>      RISCV_OP_CSR_PRE;
>>      gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
>> @@ -569,6 +584,9 @@ static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
>>
>>  static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
>>  {
>> +    if (!ctx->ext_icsr)
>> +        return false;
>> +
>>      TCGv source1, csr_store, dest, rs1_pass;
>>      RISCV_OP_CSR_PRE;
>>      gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index 8d6ab732588d..be46435b9a7b 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -55,6 +55,7 @@ typedef struct DisasContext {
>>         to reset this known value.  */
>>      int frm;
>>      bool ext_ifencei;
>> +    bool ext_icsr;
>>  } DisasContext;
>>
>>  #ifdef TARGET_RISCV64
>> @@ -762,6 +763,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>>      ctx->misa = env->misa;
>>      ctx->frm = -1;  /* unknown rounding mode */
>>      ctx->ext_ifencei = cpu->cfg.ext_ifencei;
>> +    ctx->ext_icsr = cpu->cfg.ext_icsr;
>>  }
>>
>>  static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
>> --
>> 2.21.0
>>