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s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=n4NsRNcTNd9QBFN0dr19wdrKyZyK3JwHGajMjGiM41Y=; b=d4HwCaT8tFvgqHVONhALmzTjA0SJrlkUsQoiK8e/Cf14BE0CGzkSe+KLc3+yqSDXkk RlfZ6pGp65YtJ3ivTdO+vWoGIXye11sPDwbfffzZuQUjqCl8X0e5fbAW/d0lb1knrt5R oxBqhivNyJ9EwXNYPxboQ7WZrw3fglbAYBWhog7CEx02DVsRwp4CGHgq6ljCq4PyV53k +GZLNlXB7hr4Ws71KGhFkOAgEWdhBZJxd18buiBKb72+Dt7hRXnHzV5btSGNVD34ct2u e0M5NP4omB4w1icxSfp8brtrgg5egKZh5wj3aLxXlf2eOCm8Q8E0KmnsSkyGBvavqE/P dNLQ== X-Gm-Message-State: AOAM532m8xyiWV9Dtj+cvS1b3TfWaBPpuAiHGz2K1eqQmgcXXxk+aqIw uJ1FVCbqfDlmf+gA30++vc8NyZVdUdCM+0wjUqY= X-Google-Smtp-Source: ABdhPJztV50xaOh2eg6eKeChjMZ3c3wA8Tn4t9j71RqnBkhA3tsSLaGxBrbiPV0e3E7P3lAEZKEB674giCCjQJEWyQ4= X-Received: by 2002:a05:6638:32a6:: with SMTP id f38mr7999679jav.63.1634727804702; Wed, 20 Oct 2021 04:03:24 -0700 (PDT) MIME-Version: 1.0 References: <20211020031709.359469-1-richard.henderson@linaro.org> In-Reply-To: <20211020031709.359469-1-richard.henderson@linaro.org> From: Alistair Francis Date: Wed, 20 Oct 2021 21:02:58 +1000 Message-ID: Subject: Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length To: Richard Henderson Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::d2a; envelope-from=alistair23@gmail.com; helo=mail-io1-xd2a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Alistair Francis , "qemu-devel@nongnu.org Developers" , liuzhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Oct 20, 2021 at 1:26 PM Richard Henderson wrote: > > This is a partial patch set attempting to set things in the > right direction for both the UXL and RV128 patch sets. > > > r~ > > > Changes for v6: > * Rebase on riscv-to-apply.next. > > Changes for v5: > * Fix cpu_dump, which asserted for -accel qtest. > Instead of filtering CSRs explicitly in cpu_dump, > let the riscv_csr_operations predicate do the job. > This means we won't dump S-mode registers when RVS > is not enabled, much like we currently filter on RVH. > > Changes for v4: > * Use riscv_csrrw_debug for cpu_dump. > This fixes the issue that Alistair pointed out wrt the > MSTATUS.SD bit not being correct in the dump; note that > gdbstub already uses riscv_csrrw_debug, and so did not > have a problem. > * Align the registers in cpu_dump. > > Changes for v3: > * Fix CONFIG_ typo. > * Fix ctzw typo. > * Mark get_xlen unused (clang werror) > * Compute MSTATUS_SD on demand. > > Changes for v2: > * Set mxl/sxl/uxl at reset. > * Set sxl/uxl in write_mstatus. > > > Richard Henderson (15): > target/riscv: Move cpu_get_tb_cpu_state out of line > target/riscv: Create RISCVMXL enumeration > target/riscv: Split misa.mxl and misa.ext > target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl > target/riscv: Add MXL/SXL/UXL to TB_FLAGS > target/riscv: Use REQUIRE_64BIT in amo_check64 > target/riscv: Properly check SEW in amo_op > target/riscv: Replace is_32bit with get_xl/get_xlen > target/riscv: Replace DisasContext.w with DisasContext.ol > target/riscv: Use gen_arith_per_ol for RVM > target/riscv: Adjust trans_rev8_32 for riscv64 > target/riscv: Use gen_unary_per_ol for RVB > target/riscv: Use gen_shift*_per_ol for RVB, RVI > target/riscv: Use riscv_csrrw_debug for cpu_dump > target/riscv: Compute mstatus.sd on demand Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.h | 73 +++------ > target/riscv/cpu_bits.h | 8 +- > hw/riscv/boot.c | 2 +- > linux-user/elfload.c | 2 +- > linux-user/riscv/cpu_loop.c | 2 +- > semihosting/arm-compat-semi.c | 2 +- > target/riscv/cpu.c | 195 +++++++++++++----------- > target/riscv/cpu_helper.c | 92 ++++++++++- > target/riscv/csr.c | 104 ++++++++----- > target/riscv/gdbstub.c | 10 +- > target/riscv/machine.c | 10 +- > target/riscv/monitor.c | 4 +- > target/riscv/translate.c | 174 +++++++++++++++------ > target/riscv/insn_trans/trans_rvb.c.inc | 140 +++++++++-------- > target/riscv/insn_trans/trans_rvi.c.inc | 44 +++--- > target/riscv/insn_trans/trans_rvm.c.inc | 36 ++++- > target/riscv/insn_trans/trans_rvv.c.inc | 29 ++-- > 17 files changed, 576 insertions(+), 351 deletions(-) > > -- > 2.25.1 > >