Re: [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base

From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Bin Meng <bin.meng@windriver.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base
Date: Fri, 19 Nov 2021 14:51:10 +1000	[thread overview]
Message-ID: <CAKmqyKN9MoJtfxTay2bo2n=EsQ5ZHX1MuM3NA0UHn1fzGxQ8VQ@mail.gmail.com> (raw)
In-Reply-To: <20211111155149.58172-12-zhiwei_liu@c-sky.com>

On Fri, Nov 12, 2021 at 2:05 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Use cached cur_pmmask and cur_pmbase to infer the
> current PM mode.
>
> This may decrease the TCG IR by one when pm_enabled
> is true and pm_base_enabled is false.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.h        |  3 ++-
>  target/riscv/cpu_helper.c | 25 +++++++------------------
>  target/riscv/translate.c  | 12 ++++++++----
>  3 files changed, 17 insertions(+), 23 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index fa5a6ba1c8..9fba876e08 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -411,7 +411,8 @@ FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
>  /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
>  FIELD(TB_FLAGS, XL, 13, 2)
>  /* If PointerMasking should be applied */
> -FIELD(TB_FLAGS, PM_ENABLED, 15, 1)
> +FIELD(TB_FLAGS, PM_MASK_ENABLED, 15, 1)
> +FIELD(TB_FLAGS, PM_BASE_ENABLED, 16, 1)
>
>  #ifdef TARGET_RISCV32
>  #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 8320f56d9f..a40ed6d748 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -108,26 +108,15 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>          flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
>                             get_field(env->mstatus_hs, MSTATUS_FS));
>      }
> -    if (riscv_has_ext(env, RVJ)) {
> -        int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
> -        bool pm_enabled = false;
> -        switch (priv) {
> -        case PRV_U:
> -            pm_enabled = env->mmte & U_PM_ENABLE;
> -            break;
> -        case PRV_S:
> -            pm_enabled = env->mmte & S_PM_ENABLE;
> -            break;
> -        case PRV_M:
> -            pm_enabled = env->mmte & M_PM_ENABLE;
> -            break;
> -        default:
> -            g_assert_not_reached();
> -        }
> -        flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
> -    }
>  #endif
>
> +    if (env->cur_pmmask < (xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
> +        flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
> +    }
> +    if (env->cur_pmbase != 0) {
> +        flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
> +    }
> +
>      flags = FIELD_DP32(flags, TB_FLAGS, XL, xl);
>
>      *pflags = flags;
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index fd75f7c4bc..10c16e759d 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -87,7 +87,8 @@ typedef struct DisasContext {
>      /* Space for 3 operands plus 1 extra for address computation. */
>      TCGv temp[4];
>      /* PointerMasking extension */
> -    bool pm_enabled;
> +    bool pm_mask_enabled;
> +    bool pm_base_enabled;
>  } DisasContext;
>
>  static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> @@ -291,12 +292,14 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
>      TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>
>      tcg_gen_addi_tl(addr, src1, imm);
> -    if (ctx->pm_enabled) {
> +    if (ctx->pm_mask_enabled) {
>          tcg_gen_and_tl(addr, addr, pm_mask);
> -        tcg_gen_or_tl(addr, addr, pm_base);
>      } else if (get_xl(ctx) == MXL_RV32) {
>          tcg_gen_ext32u_tl(addr, addr);
>      }
> +    if (ctx->pm_base_enabled) {
> +        tcg_gen_or_tl(addr, addr, pm_base);
> +    }
>      return addr;
>  }
>
> @@ -643,7 +646,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>      ctx->cs = cs;
>      ctx->ntemp = 0;
>      memset(ctx->temp, 0, sizeof(ctx->temp));
> -    ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
> +    ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
> +    ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
>      ctx->zero = tcg_constant_tl(0);
>  }
>
> --
> 2.25.1
>
>