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X-Received-From: 2607:f8b0:4864:20::a44 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, "open list:RISC-V" , Richard Henderson , "qemu-devel@nongnu.org Developers" , wxy194768@alibaba-inc.com, Chih-Min Chao , wenmeng_zhang@c-sky.com, Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Mar 17, 2020 at 8:33 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 25 ++++++++++++ > target/riscv/insn32.decode | 9 +++++ > target/riscv/insn_trans/trans_rvv.inc.c | 11 ++++++ > target/riscv/vector_helper.c | 51 +++++++++++++++++++++++++ > 4 files changed, 96 insertions(+) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 72c733bf49..4373e9e8c2 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -372,3 +372,28 @@ DEF_HELPER_6(vmsbc_vxm_b, void, ptr, ptr, tl, ptr, env, i32) > DEF_HELPER_6(vmsbc_vxm_h, void, ptr, ptr, tl, ptr, env, i32) > DEF_HELPER_6(vmsbc_vxm_w, void, ptr, ptr, tl, ptr, env, i32) > DEF_HELPER_6(vmsbc_vxm_d, void, ptr, ptr, tl, ptr, env, i32) > + > +DEF_HELPER_6(vand_vv_b, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vand_vv_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vand_vv_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vand_vv_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vor_vv_b, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vor_vv_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vor_vv_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vor_vv_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vxor_vv_b, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vxor_vv_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vxor_vv_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vxor_vv_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vand_vx_b, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vand_vx_h, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vand_vx_w, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vand_vx_d, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vor_vx_b, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vor_vx_h, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vor_vx_w, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vor_vx_d, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vxor_vx_b, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vxor_vx_h, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vxor_vx_w, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vxor_vx_d, void, ptr, ptr, tl, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 022c8ea18b..3ad6724632 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -311,6 +311,15 @@ vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1 > vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1 > vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1 > vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1 > +vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm > +vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm > +vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm > +vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm > +vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm > +vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm > +vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm > +vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm > +vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm > > vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c > index 4562d5f14f..b4ba6d83f3 100644 > --- a/target/riscv/insn_trans/trans_rvv.inc.c > +++ b/target/riscv/insn_trans/trans_rvv.inc.c > @@ -1247,3 +1247,14 @@ GEN_OPIVX_TRANS(vmsbc_vxm, opivx_vmadc_check) > > GEN_OPIVI_TRANS(vadc_vim, 0, vadc_vxm, opivx_vadc_check) > GEN_OPIVI_TRANS(vmadc_vim, 0, vmadc_vxm, opivx_vmadc_check) > + > +/* Vector Bitwise Logical Instructions */ > +GEN_OPIVV_GVEC_TRANS(vand_vv, and) > +GEN_OPIVV_GVEC_TRANS(vor_vv, or) > +GEN_OPIVV_GVEC_TRANS(vxor_vv, xor) > +GEN_OPIVX_GVEC_TRANS(vand_vx, ands) > +GEN_OPIVX_GVEC_TRANS(vor_vx, ors) > +GEN_OPIVX_GVEC_TRANS(vxor_vx, xors) > +GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi) > +GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori) > +GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori) > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 9913dcbea2..470bf079b2 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -1235,3 +1235,54 @@ GEN_VEXT_VMADC_VXM(vmsbc_vxm_b, uint8_t, H1, DO_MSBC) > GEN_VEXT_VMADC_VXM(vmsbc_vxm_h, uint16_t, H2, DO_MSBC) > GEN_VEXT_VMADC_VXM(vmsbc_vxm_w, uint32_t, H4, DO_MSBC) > GEN_VEXT_VMADC_VXM(vmsbc_vxm_d, uint64_t, H8, DO_MSBC) > + > +/* Vector Bitwise Logical Instructions */ > +RVVCALL(OPIVV2, vand_vv_b, OP_SSS_B, H1, H1, H1, DO_AND) > +RVVCALL(OPIVV2, vand_vv_h, OP_SSS_H, H2, H2, H2, DO_AND) > +RVVCALL(OPIVV2, vand_vv_w, OP_SSS_W, H4, H4, H4, DO_AND) > +RVVCALL(OPIVV2, vand_vv_d, OP_SSS_D, H8, H8, H8, DO_AND) > +RVVCALL(OPIVV2, vor_vv_b, OP_SSS_B, H1, H1, H1, DO_OR) > +RVVCALL(OPIVV2, vor_vv_h, OP_SSS_H, H2, H2, H2, DO_OR) > +RVVCALL(OPIVV2, vor_vv_w, OP_SSS_W, H4, H4, H4, DO_OR) > +RVVCALL(OPIVV2, vor_vv_d, OP_SSS_D, H8, H8, H8, DO_OR) > +RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR) > +RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR) > +RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR) > +RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR) > +GEN_VEXT_VV(vand_vv_b, 1, 1, clearb) > +GEN_VEXT_VV(vand_vv_h, 2, 2, clearh) > +GEN_VEXT_VV(vand_vv_w, 4, 4, clearl) > +GEN_VEXT_VV(vand_vv_d, 8, 8, clearq) > +GEN_VEXT_VV(vor_vv_b, 1, 1, clearb) > +GEN_VEXT_VV(vor_vv_h, 2, 2, clearh) > +GEN_VEXT_VV(vor_vv_w, 4, 4, clearl) > +GEN_VEXT_VV(vor_vv_d, 8, 8, clearq) > +GEN_VEXT_VV(vxor_vv_b, 1, 1, clearb) > +GEN_VEXT_VV(vxor_vv_h, 2, 2, clearh) > +GEN_VEXT_VV(vxor_vv_w, 4, 4, clearl) > +GEN_VEXT_VV(vxor_vv_d, 8, 8, clearq) > + > +RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND) > +RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND) > +RVVCALL(OPIVX2, vand_vx_w, OP_SSS_W, H4, H4, DO_AND) > +RVVCALL(OPIVX2, vand_vx_d, OP_SSS_D, H8, H8, DO_AND) > +RVVCALL(OPIVX2, vor_vx_b, OP_SSS_B, H1, H1, DO_OR) > +RVVCALL(OPIVX2, vor_vx_h, OP_SSS_H, H2, H2, DO_OR) > +RVVCALL(OPIVX2, vor_vx_w, OP_SSS_W, H4, H4, DO_OR) > +RVVCALL(OPIVX2, vor_vx_d, OP_SSS_D, H8, H8, DO_OR) > +RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR) > +RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR) > +RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR) > +RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR) > +GEN_VEXT_VX(vand_vx_b, 1, 1, clearb) > +GEN_VEXT_VX(vand_vx_h, 2, 2, clearh) > +GEN_VEXT_VX(vand_vx_w, 4, 4, clearl) > +GEN_VEXT_VX(vand_vx_d, 8, 8, clearq) > +GEN_VEXT_VX(vor_vx_b, 1, 1, clearb) > +GEN_VEXT_VX(vor_vx_h, 2, 2, clearh) > +GEN_VEXT_VX(vor_vx_w, 4, 4, clearl) > +GEN_VEXT_VX(vor_vx_d, 8, 8, clearq) > +GEN_VEXT_VX(vxor_vx_b, 1, 1, clearb) > +GEN_VEXT_VX(vxor_vx_h, 2, 2, clearh) > +GEN_VEXT_VX(vxor_vx_w, 4, 4, clearl) > +GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq) > -- > 2.23.0 >