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Thu, 16 Dec 2021 19:17:30 -0800 (PST) MIME-Version: 1.0 References: <20211211041917.135345-1-anup.patel@wdc.com> <20211211041917.135345-9-anup.patel@wdc.com> In-Reply-To: <20211211041917.135345-9-anup.patel@wdc.com> From: Alistair Francis Date: Fri, 17 Dec 2021 13:17:04 +1000 Message-ID: Subject: Re: [PATCH v5 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback To: Anup Patel Content-Type: text/plain; charset="UTF-8" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::d30 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::d30; envelope-from=alistair23@gmail.com; helo=mail-io1-xd30.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:RISC-V" , Sagar Karandikar , Anup Patel , "qemu-devel@nongnu.org Developers" , Alistair Francis , Atish Patra , Palmer Dabbelt , Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sat, Dec 11, 2021 at 2:26 PM Anup Patel wrote: > > The AIA device emulation (such as AIA IMSIC) should be able to set > (or provide) AIA ireg read-modify-write callback for each privilege > level of a RISC-V HART. > > Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.h | 23 +++++++++++++++++++++++ > target/riscv/cpu_helper.c | 14 ++++++++++++++ > 2 files changed, 37 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 6e5b6acd44..df1d792951 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -240,6 +240,22 @@ struct CPURISCVState { > uint64_t (*rdtime_fn)(uint32_t); > uint32_t rdtime_fn_arg; > > + /* machine specific AIA ireg read-modify-write callback */ > +#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ > + ((((__xlen) & 0xff) << 24) | \ > + (((__vgein) & 0x3f) << 20) | \ > + (((__virt) & 0x1) << 18) | \ > + (((__priv) & 0x3) << 16) | \ > + (__isel & 0xffff)) > +#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) > +#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) > +#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) > +#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) > +#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) > + int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, > + target_ulong *val, target_ulong new_val, target_ulong write_mask); > + void *aia_ireg_rmw_fn_arg[4]; > + > /* True if in debugger mode. */ > bool debugger; > > @@ -391,6 +407,13 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); > #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ > void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), > uint32_t arg); > +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, > + int (*rmw_fn)(void *arg, > + target_ulong reg, > + target_ulong *val, > + target_ulong new_val, > + target_ulong write_mask), > + void *rmw_fn_arg); > #endif > void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 1fa9f0e584..57c07ba1a4 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -364,6 +364,20 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), > env->rdtime_fn_arg = arg; > } > > +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, > + int (*rmw_fn)(void *arg, > + target_ulong reg, > + target_ulong *val, > + target_ulong new_val, > + target_ulong write_mask), > + void *rmw_fn_arg) > +{ > + if (priv <= PRV_M) { > + env->aia_ireg_rmw_fn[priv] = rmw_fn; > + env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; > + } > +} > + > void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) > { > if (newpriv > PRV_M) { > -- > 2.25.1 > >