From: Alistair Francis <alistair23@gmail.com>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: "Fam Zheng" <fam@euphon.net>,
"open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
robert.foley@linaro.org,
"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
stefanb@linux.vnet.ibm.com,
"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
robhenry@microsoft.com,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
aaron@os.amperecomputing.com, "Emilio G. Cota" <cota@braap.org>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Daniel P. Berrange" <berrange@redhat.com>,
"Stefan Hajnoczi" <stefanha@redhat.com>,
peter.puhov@linaro.org,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
kuhn.chenqun@huawei.com
Subject: Re: [PATCH v2 14/19] target/riscv: progressively load the instruction during decode
Date: Thu, 13 Feb 2020 17:23:24 -0800 [thread overview]
Message-ID: <CAKmqyKNj2De1hRz3XU88rVnkZ4TytwcDTNuWXYB-Wa38rWv48Q@mail.gmail.com> (raw)
In-Reply-To: <20200213225109.13120-15-alex.bennee@linaro.org>
On Thu, Feb 13, 2020 at 3:08 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> The plugin system would throw up a harmless warning when it detected
> that a disassembly of an instruction didn't use all it's bytes. Fix
> the riscv decoder to only load the instruction bytes it needs as it
> needs them.
>
> This drops opcode from the ctx in favour if passing the appropriately
> sized opcode down a few levels of the decode.
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
> v2
> - use extract16 for uint16_t opcodes
>
> squash! target/riscv: progressively load the instruction during decode
> ---
> target/riscv/instmap.h | 8 ++++----
> target/riscv/translate.c | 40 +++++++++++++++++++++-------------------
> 2 files changed, 25 insertions(+), 23 deletions(-)
>
> diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h
> index f8ad7d60fd5..40b6d2b64de 100644
> --- a/target/riscv/instmap.h
> +++ b/target/riscv/instmap.h
> @@ -344,8 +344,8 @@ enum {
> #define GET_C_LW_IMM(inst) ((extract32(inst, 6, 1) << 2) \
> | (extract32(inst, 10, 3) << 3) \
> | (extract32(inst, 5, 1) << 6))
> -#define GET_C_LD_IMM(inst) ((extract32(inst, 10, 3) << 3) \
> - | (extract32(inst, 5, 2) << 6))
> +#define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \
> + | (extract16(inst, 5, 2) << 6))
> #define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \
> | (extract32(inst, 11, 1) << 4) \
> | (extract32(inst, 2, 1) << 5) \
> @@ -363,7 +363,7 @@ enum {
> #define GET_C_RD(inst) GET_RD(inst)
> #define GET_C_RS1(inst) GET_RD(inst)
> #define GET_C_RS2(inst) extract32(inst, 2, 5)
> -#define GET_C_RS1S(inst) (8 + extract32(inst, 7, 3))
> -#define GET_C_RS2S(inst) (8 + extract32(inst, 2, 3))
> +#define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3))
> +#define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3))
>
> #endif
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 14dc71156be..d5de7f468a7 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -44,7 +44,6 @@ typedef struct DisasContext {
> /* pc_succ_insn points to the instruction following base.pc_next */
> target_ulong pc_succ_insn;
> target_ulong priv_ver;
> - uint32_t opcode;
> uint32_t mstatus_fs;
> uint32_t misa;
> uint32_t mem_idx;
> @@ -492,45 +491,45 @@ static void gen_set_rm(DisasContext *ctx, int rm)
> tcg_temp_free_i32(t0);
> }
>
> -static void decode_RV32_64C0(DisasContext *ctx)
> +static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
> {
> - uint8_t funct3 = extract32(ctx->opcode, 13, 3);
> - uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode);
> - uint8_t rs1s = GET_C_RS1S(ctx->opcode);
> + uint8_t funct3 = extract16(opcode, 13, 3);
> + uint8_t rd_rs2 = GET_C_RS2S(opcode);
> + uint8_t rs1s = GET_C_RS1S(opcode);
>
> switch (funct3) {
> case 3:
> #if defined(TARGET_RISCV64)
> /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
> gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
> - GET_C_LD_IMM(ctx->opcode));
> + GET_C_LD_IMM(opcode));
> #else
> /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
> gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
> - GET_C_LW_IMM(ctx->opcode));
> + GET_C_LW_IMM(opcode));
> #endif
> break;
> case 7:
> #if defined(TARGET_RISCV64)
> /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
> gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
> - GET_C_LD_IMM(ctx->opcode));
> + GET_C_LD_IMM(opcode));
> #else
> /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
> gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
> - GET_C_LW_IMM(ctx->opcode));
> + GET_C_LW_IMM(opcode));
> #endif
> break;
> }
> }
>
> -static void decode_RV32_64C(DisasContext *ctx)
> +static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
> {
> - uint8_t op = extract32(ctx->opcode, 0, 2);
> + uint8_t op = extract16(opcode, 0, 2);
>
> switch (op) {
> case 0:
> - decode_RV32_64C0(ctx);
> + decode_RV32_64C0(ctx, opcode);
> break;
> }
> }
> @@ -709,22 +708,25 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
> /* Include the auto-generated decoder for 16 bit insn */
> #include "decode_insn16.inc.c"
>
> -static void decode_opc(DisasContext *ctx)
> +static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
> {
> /* check for compressed insn */
> - if (extract32(ctx->opcode, 0, 2) != 3) {
> + if (extract16(opcode, 0, 2) != 3) {
> if (!has_ext(ctx, RVC)) {
> gen_exception_illegal(ctx);
> } else {
> ctx->pc_succ_insn = ctx->base.pc_next + 2;
> - if (!decode_insn16(ctx, ctx->opcode)) {
> + if (!decode_insn16(ctx, opcode)) {
> /* fall back to old decoder */
> - decode_RV32_64C(ctx);
> + decode_RV32_64C(ctx, opcode);
> }
> }
> } else {
> + uint32_t opcode32 = opcode;
> + opcode32 = deposit32(opcode32, 16, 16,
> + translator_lduw(env, ctx->base.pc_next + 2));
> ctx->pc_succ_insn = ctx->base.pc_next + 4;
> - if (!decode_insn32(ctx, ctx->opcode)) {
> + if (!decode_insn32(ctx, opcode32)) {
> gen_exception_illegal(ctx);
> }
> }
> @@ -776,9 +778,9 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> CPURISCVState *env = cpu->env_ptr;
> + uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next);
>
> - ctx->opcode = translator_ldl(env, ctx->base.pc_next);
> - decode_opc(ctx);
> + decode_opc(env, ctx, opcode16);
> ctx->base.pc_next = ctx->pc_succ_insn;
>
> if (ctx->base.is_jmp == DISAS_NEXT) {
> --
> 2.20.1
>
>
next prev parent reply other threads:[~2020-02-14 1:33 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-13 22:50 [PATCH v2 00/19] testing and plugin updates Alex Bennée
2020-02-13 22:50 ` [PATCH v2 01/19] tests/tcg: include a skip runner for pauth3 with plugins Alex Bennée
2020-02-14 19:41 ` Robert Foley
2020-02-13 22:50 ` [PATCH v2 02/19] tests/rcutorture: update usage hint Alex Bennée
2020-02-13 22:50 ` [PATCH v2 03/19] tests/rcutorture: better document locking of stats Alex Bennée
2020-02-13 22:50 ` [PATCH v2 04/19] tests/rcutorture: mild documenting refactor of update thread Alex Bennée
2020-02-14 9:18 ` Paolo Bonzini
2020-02-13 22:50 ` [PATCH v2 05/19] travis.yml: Test the s390-ccw build, too Alex Bennée
2020-02-13 22:50 ` [PATCH v2 06/19] travis.yml: Fix Travis YAML configuration warnings Alex Bennée
2020-02-13 22:50 ` [PATCH v2 07/19] travis.yml: single-thread build-tcg stages Alex Bennée
2020-02-14 12:15 ` Philippe Mathieu-Daudé
2020-02-13 22:50 ` [PATCH v2 08/19] tests/iotests: be a little more forgiving on the size test Alex Bennée
2020-02-13 22:50 ` [PATCH v2 09/19] tracing: only allow -trace to override -D if set Alex Bennée
2020-02-14 18:19 ` Robert Foley
2020-02-13 22:51 ` [PATCH v2 10/19] docs/devel: document query handle lifetimes Alex Bennée
2020-02-13 22:51 ` [PATCH v2 11/19] plugins/core: add missing break in cb_to_tcg_flags Alex Bennée
2020-02-14 0:52 ` Philippe Mathieu-Daudé
2020-02-13 22:51 ` [PATCH v2 12/19] tests/plugin: prevent uninitialized warning Alex Bennée
2020-02-13 22:51 ` [PATCH v2 13/19] qemu/bitops.h: Add extract8 and extract16 Alex Bennée
2020-02-13 22:51 ` [PATCH v2 14/19] target/riscv: progressively load the instruction during decode Alex Bennée
2020-02-14 1:23 ` Alistair Francis [this message]
2020-02-14 19:34 ` Robert Foley
2020-02-13 22:51 ` [PATCH v2 15/19] tests/plugins: make howvec clean-up after itself Alex Bennée
2020-02-13 22:51 ` [PATCH v2 16/19] tests/tcg: give debug builds a little bit longer Alex Bennée
2020-02-14 0:50 ` Philippe Mathieu-Daudé
2020-02-13 22:51 ` [PATCH v2 17/19] tcg: save vaddr temp for plugin usage Alex Bennée
2020-02-16 9:23 ` Richard Henderson
2020-02-23 3:06 ` Emilio G. Cota
2020-02-13 22:51 ` [PATCH v2 18/19] tests/tcg: fix typo in configure.sh test for v8.3 Alex Bennée
2020-02-14 0:50 ` Philippe Mathieu-Daudé
2020-02-16 9:24 ` Richard Henderson
2020-02-13 22:51 ` [PATCH v2 19/19] tests/tcg: take into account expected clashes pauth-4 Alex Bennée
2020-02-14 19:12 ` Robert Foley
2020-02-16 9:30 ` Richard Henderson
2020-02-13 23:16 ` [PATCH v2 00/19] testing and plugin updates no-reply
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