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X-Received-From: 2a00:1450:4864:20::142 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Sagar Karandikar , Bastian Koppelmann , Richard Henderson , "qemu-devel@nongnu.org Developers" , "Emilio G. Cota" , Alistair Francis , =?UTF-8?B?QWxleCBCZW5uw6ll?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Jun 19, 2019 at 3:50 AM Palmer Dabbelt wrote: > > On Mon, 17 Jun 2019 15:38:45 PDT (-0700), richard.henderson@linaro.org wr= ote: > > On 6/14/19 10:11 AM, Alex Benn=C3=A9e wrote: > >> +++ b/target/riscv/translate.c > >> @@ -793,7 +793,7 @@ static void riscv_tr_translate_insn(DisasContextBa= se *dcbase, CPUState *cpu) > >> DisasContext *ctx =3D container_of(dcbase, DisasContext, base); > >> CPURISCVState *env =3D cpu->env_ptr; > >> > >> - ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); > >> + ctx->opcode =3D translator_ldl(env, ctx->base.pc_next); > > > > I'll note for the riscv folks that this is an existing bug, reading too= much in > > the case of an RVC instruction. This could well matter for the last 2-= byte > > instruction at the end of a page. > > > > Reviewed-by: Richard Henderson > > Thanks for pointing this out. I'm checking the ISA semantics with Andrew= to > make sure I've got it right, as there's some implicit wording in the docu= ment > that doesn't quite do what I'd expect it to. Did we figure out what to do here? Alistair >