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* [PATCH 1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
@ 2020-05-21 14:42 Bin Meng
  2020-05-21 14:42 ` [PATCH 2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions Bin Meng
  2020-05-21 14:48 ` [PATCH 1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions Philippe Mathieu-Daudé
  0 siblings, 2 replies; 6+ messages in thread
From: Bin Meng @ 2020-05-21 14:42 UTC (permalink / raw)
  To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
	Sagar Karandikar, qemu-devel, qemu-riscv
  Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

To keep consistency with the machine* functions, remove the riscv_
prefix of the soc* functions.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 hw/riscv/sifive_u.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 4299bdf..f9fef2b 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -481,7 +481,7 @@ static void sifive_u_machine_init_register_types(void)
 
 type_init(sifive_u_machine_init_register_types)
 
-static void riscv_sifive_u_soc_init(Object *obj)
+static void sifive_u_soc_instance_init(Object *obj)
 {
     MachineState *ms = MACHINE(qdev_get_machine());
     SiFiveUSoCState *s = RISCV_U_SOC(obj);
@@ -520,7 +520,7 @@ static void riscv_sifive_u_soc_init(Object *obj)
                           TYPE_CADENCE_GEM);
 }
 
-static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
+static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
 {
     MachineState *ms = MACHINE(qdev_get_machine());
     SiFiveUSoCState *s = RISCV_U_SOC(dev);
@@ -635,32 +635,32 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
         memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
 }
 
-static Property riscv_sifive_u_soc_props[] = {
+static Property sifive_u_soc_props[] = {
     DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
     DEFINE_PROP_END_OF_LIST()
 };
 
-static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
+static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
-    device_class_set_props(dc, riscv_sifive_u_soc_props);
-    dc->realize = riscv_sifive_u_soc_realize;
+    device_class_set_props(dc, sifive_u_soc_props);
+    dc->realize = sifive_u_soc_realize;
     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
     dc->user_creatable = false;
 }
 
-static const TypeInfo riscv_sifive_u_soc_type_info = {
+static const TypeInfo sifive_u_soc_type_info = {
     .name = TYPE_RISCV_U_SOC,
     .parent = TYPE_DEVICE,
     .instance_size = sizeof(SiFiveUSoCState),
-    .instance_init = riscv_sifive_u_soc_init,
-    .class_init = riscv_sifive_u_soc_class_init,
+    .instance_init = sifive_u_soc_instance_init,
+    .class_init = sifive_u_soc_class_init,
 };
 
-static void riscv_sifive_u_soc_register_types(void)
+static void sifive_u_soc_register_types(void)
 {
-    type_register_static(&riscv_sifive_u_soc_type_info);
+    type_register_static(&sifive_u_soc_type_info);
 }
 
-type_init(riscv_sifive_u_soc_register_types)
+type_init(sifive_u_soc_register_types)
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions
  2020-05-21 14:42 [PATCH 1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions Bin Meng
@ 2020-05-21 14:42 ` Bin Meng
  2020-05-21 14:48   ` Philippe Mathieu-Daudé
  2020-05-26 16:50   ` Alistair Francis
  2020-05-21 14:48 ` [PATCH 1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions Philippe Mathieu-Daudé
  1 sibling, 2 replies; 6+ messages in thread
From: Bin Meng @ 2020-05-21 14:42 UTC (permalink / raw)
  To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
	Sagar Karandikar, qemu-devel, qemu-riscv
  Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

Remove the riscv_ prefix of the machine* functions.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 hw/riscv/virt.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index c695a44..f1d6b61 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -471,7 +471,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
     return dev;
 }
 
-static void riscv_virt_board_init(MachineState *machine)
+static void virt_machine_init(MachineState *machine)
 {
     const struct MemmapEntry *memmap = virt_memmap;
     RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
@@ -632,32 +632,32 @@ static void riscv_virt_board_init(MachineState *machine)
     g_free(plic_hart_config);
 }
 
-static void riscv_virt_machine_instance_init(Object *obj)
+static void virt_machine_instance_init(Object *obj)
 {
 }
 
-static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
+static void virt_machine_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
 
     mc->desc = "RISC-V VirtIO board";
-    mc->init = riscv_virt_board_init;
+    mc->init = virt_machine_init;
     mc->max_cpus = 8;
     mc->default_cpu_type = VIRT_CPU;
     mc->pci_allow_0_address = true;
 }
 
-static const TypeInfo riscv_virt_machine_typeinfo = {
+static const TypeInfo virt_machine_typeinfo = {
     .name       = MACHINE_TYPE_NAME("virt"),
     .parent     = TYPE_MACHINE,
-    .class_init = riscv_virt_machine_class_init,
-    .instance_init = riscv_virt_machine_instance_init,
+    .class_init = virt_machine_class_init,
+    .instance_init = virt_machine_instance_init,
     .instance_size = sizeof(RISCVVirtState),
 };
 
-static void riscv_virt_machine_init_register_types(void)
+static void virt_machine_init_register_types(void)
 {
-    type_register_static(&riscv_virt_machine_typeinfo);
+    type_register_static(&virt_machine_typeinfo);
 }
 
-type_init(riscv_virt_machine_init_register_types)
+type_init(virt_machine_init_register_types)
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
  2020-05-21 14:42 [PATCH 1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions Bin Meng
  2020-05-21 14:42 ` [PATCH 2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions Bin Meng
@ 2020-05-21 14:48 ` Philippe Mathieu-Daudé
  2020-05-21 22:09   ` Alistair Francis
  1 sibling, 1 reply; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-21 14:48 UTC (permalink / raw)
  To: Bin Meng, Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
	Sagar Karandikar, qemu-devel, qemu-riscv
  Cc: Bin Meng

On 5/21/20 4:42 PM, Bin Meng wrote:
> From: Bin Meng <bin.meng@windriver.com>
> 
> To keep consistency with the machine* functions, remove the riscv_
> prefix of the soc* functions.
> 
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
> 
>   hw/riscv/sifive_u.c | 24 ++++++++++++------------
>   1 file changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 4299bdf..f9fef2b 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -481,7 +481,7 @@ static void sifive_u_machine_init_register_types(void)
>   
>   type_init(sifive_u_machine_init_register_types)
>   
> -static void riscv_sifive_u_soc_init(Object *obj)
> +static void sifive_u_soc_instance_init(Object *obj)
>   {
>       MachineState *ms = MACHINE(qdev_get_machine());
>       SiFiveUSoCState *s = RISCV_U_SOC(obj);
> @@ -520,7 +520,7 @@ static void riscv_sifive_u_soc_init(Object *obj)
>                             TYPE_CADENCE_GEM);
>   }
>   
> -static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
> +static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
>   {
>       MachineState *ms = MACHINE(qdev_get_machine());
>       SiFiveUSoCState *s = RISCV_U_SOC(dev);
> @@ -635,32 +635,32 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
>           memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
>   }
>   
> -static Property riscv_sifive_u_soc_props[] = {
> +static Property sifive_u_soc_props[] = {
>       DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
>       DEFINE_PROP_END_OF_LIST()
>   };
>   
> -static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
> +static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
>   {
>       DeviceClass *dc = DEVICE_CLASS(oc);
>   
> -    device_class_set_props(dc, riscv_sifive_u_soc_props);
> -    dc->realize = riscv_sifive_u_soc_realize;
> +    device_class_set_props(dc, sifive_u_soc_props);
> +    dc->realize = sifive_u_soc_realize;
>       /* Reason: Uses serial_hds in realize function, thus can't be used twice */
>       dc->user_creatable = false;
>   }
>   
> -static const TypeInfo riscv_sifive_u_soc_type_info = {
> +static const TypeInfo sifive_u_soc_type_info = {
>       .name = TYPE_RISCV_U_SOC,
>       .parent = TYPE_DEVICE,
>       .instance_size = sizeof(SiFiveUSoCState),
> -    .instance_init = riscv_sifive_u_soc_init,
> -    .class_init = riscv_sifive_u_soc_class_init,
> +    .instance_init = sifive_u_soc_instance_init,
> +    .class_init = sifive_u_soc_class_init,
>   };
>   
> -static void riscv_sifive_u_soc_register_types(void)
> +static void sifive_u_soc_register_types(void)
>   {
> -    type_register_static(&riscv_sifive_u_soc_type_info);
> +    type_register_static(&sifive_u_soc_type_info);
>   }
>   
> -type_init(riscv_sifive_u_soc_register_types)
> +type_init(sifive_u_soc_register_types)
> 

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>



^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions
  2020-05-21 14:42 ` [PATCH 2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions Bin Meng
@ 2020-05-21 14:48   ` Philippe Mathieu-Daudé
  2020-05-26 16:50   ` Alistair Francis
  1 sibling, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-21 14:48 UTC (permalink / raw)
  To: Bin Meng, Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
	Sagar Karandikar, qemu-devel, qemu-riscv
  Cc: Bin Meng

On 5/21/20 4:42 PM, Bin Meng wrote:
> From: Bin Meng <bin.meng@windriver.com>
> 
> Remove the riscv_ prefix of the machine* functions.
> 
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
> 
>   hw/riscv/virt.c | 20 ++++++++++----------
>   1 file changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index c695a44..f1d6b61 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -471,7 +471,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
>       return dev;
>   }
>   
> -static void riscv_virt_board_init(MachineState *machine)
> +static void virt_machine_init(MachineState *machine)
>   {
>       const struct MemmapEntry *memmap = virt_memmap;
>       RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
> @@ -632,32 +632,32 @@ static void riscv_virt_board_init(MachineState *machine)
>       g_free(plic_hart_config);
>   }
>   
> -static void riscv_virt_machine_instance_init(Object *obj)
> +static void virt_machine_instance_init(Object *obj)
>   {
>   }
>   
> -static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
> +static void virt_machine_class_init(ObjectClass *oc, void *data)
>   {
>       MachineClass *mc = MACHINE_CLASS(oc);
>   
>       mc->desc = "RISC-V VirtIO board";
> -    mc->init = riscv_virt_board_init;
> +    mc->init = virt_machine_init;
>       mc->max_cpus = 8;
>       mc->default_cpu_type = VIRT_CPU;
>       mc->pci_allow_0_address = true;
>   }
>   
> -static const TypeInfo riscv_virt_machine_typeinfo = {
> +static const TypeInfo virt_machine_typeinfo = {
>       .name       = MACHINE_TYPE_NAME("virt"),
>       .parent     = TYPE_MACHINE,
> -    .class_init = riscv_virt_machine_class_init,
> -    .instance_init = riscv_virt_machine_instance_init,
> +    .class_init = virt_machine_class_init,
> +    .instance_init = virt_machine_instance_init,
>       .instance_size = sizeof(RISCVVirtState),
>   };
>   
> -static void riscv_virt_machine_init_register_types(void)
> +static void virt_machine_init_register_types(void)
>   {
> -    type_register_static(&riscv_virt_machine_typeinfo);
> +    type_register_static(&virt_machine_typeinfo);
>   }
>   
> -type_init(riscv_virt_machine_init_register_types)
> +type_init(virt_machine_init_register_types)
> 

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>



^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
  2020-05-21 14:48 ` [PATCH 1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions Philippe Mathieu-Daudé
@ 2020-05-21 22:09   ` Alistair Francis
  0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2020-05-21 22:09 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé
  Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
	Palmer Dabbelt, qemu-devel@nongnu.org Developers,
	Alistair Francis, Bin Meng

On Thu, May 21, 2020 at 7:48 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 5/21/20 4:42 PM, Bin Meng wrote:
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > To keep consistency with the machine* functions, remove the riscv_
> > prefix of the soc* functions.
> >
> > Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> > ---
> >
> >   hw/riscv/sifive_u.c | 24 ++++++++++++------------
> >   1 file changed, 12 insertions(+), 12 deletions(-)
> >
> > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> > index 4299bdf..f9fef2b 100644
> > --- a/hw/riscv/sifive_u.c
> > +++ b/hw/riscv/sifive_u.c
> > @@ -481,7 +481,7 @@ static void sifive_u_machine_init_register_types(void)
> >
> >   type_init(sifive_u_machine_init_register_types)
> >
> > -static void riscv_sifive_u_soc_init(Object *obj)
> > +static void sifive_u_soc_instance_init(Object *obj)
> >   {
> >       MachineState *ms = MACHINE(qdev_get_machine());
> >       SiFiveUSoCState *s = RISCV_U_SOC(obj);
> > @@ -520,7 +520,7 @@ static void riscv_sifive_u_soc_init(Object *obj)
> >                             TYPE_CADENCE_GEM);
> >   }
> >
> > -static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
> > +static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> >   {
> >       MachineState *ms = MACHINE(qdev_get_machine());
> >       SiFiveUSoCState *s = RISCV_U_SOC(dev);
> > @@ -635,32 +635,32 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
> >           memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
> >   }
> >
> > -static Property riscv_sifive_u_soc_props[] = {
> > +static Property sifive_u_soc_props[] = {
> >       DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
> >       DEFINE_PROP_END_OF_LIST()
> >   };
> >
> > -static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
> > +static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
> >   {
> >       DeviceClass *dc = DEVICE_CLASS(oc);
> >
> > -    device_class_set_props(dc, riscv_sifive_u_soc_props);
> > -    dc->realize = riscv_sifive_u_soc_realize;
> > +    device_class_set_props(dc, sifive_u_soc_props);
> > +    dc->realize = sifive_u_soc_realize;
> >       /* Reason: Uses serial_hds in realize function, thus can't be used twice */
> >       dc->user_creatable = false;
> >   }
> >
> > -static const TypeInfo riscv_sifive_u_soc_type_info = {
> > +static const TypeInfo sifive_u_soc_type_info = {
> >       .name = TYPE_RISCV_U_SOC,
> >       .parent = TYPE_DEVICE,
> >       .instance_size = sizeof(SiFiveUSoCState),
> > -    .instance_init = riscv_sifive_u_soc_init,
> > -    .class_init = riscv_sifive_u_soc_class_init,
> > +    .instance_init = sifive_u_soc_instance_init,
> > +    .class_init = sifive_u_soc_class_init,
> >   };
> >
> > -static void riscv_sifive_u_soc_register_types(void)
> > +static void sifive_u_soc_register_types(void)
> >   {
> > -    type_register_static(&riscv_sifive_u_soc_type_info);
> > +    type_register_static(&sifive_u_soc_type_info);
> >   }
> >
> > -type_init(riscv_sifive_u_soc_register_types)
> > +type_init(sifive_u_soc_register_types)
> >
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
>


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions
  2020-05-21 14:42 ` [PATCH 2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions Bin Meng
  2020-05-21 14:48   ` Philippe Mathieu-Daudé
@ 2020-05-26 16:50   ` Alistair Francis
  1 sibling, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2020-05-26 16:50 UTC (permalink / raw)
  To: Bin Meng
  Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
	Palmer Dabbelt, qemu-devel@nongnu.org Developers,
	Alistair Francis

On Thu, May 21, 2020 at 7:42 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Remove the riscv_ prefix of the machine* functions.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/riscv/virt.c | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index c695a44..f1d6b61 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -471,7 +471,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
>      return dev;
>  }
>
> -static void riscv_virt_board_init(MachineState *machine)
> +static void virt_machine_init(MachineState *machine)
>  {
>      const struct MemmapEntry *memmap = virt_memmap;
>      RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
> @@ -632,32 +632,32 @@ static void riscv_virt_board_init(MachineState *machine)
>      g_free(plic_hart_config);
>  }
>
> -static void riscv_virt_machine_instance_init(Object *obj)
> +static void virt_machine_instance_init(Object *obj)
>  {
>  }
>
> -static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
> +static void virt_machine_class_init(ObjectClass *oc, void *data)
>  {
>      MachineClass *mc = MACHINE_CLASS(oc);
>
>      mc->desc = "RISC-V VirtIO board";
> -    mc->init = riscv_virt_board_init;
> +    mc->init = virt_machine_init;
>      mc->max_cpus = 8;
>      mc->default_cpu_type = VIRT_CPU;
>      mc->pci_allow_0_address = true;
>  }
>
> -static const TypeInfo riscv_virt_machine_typeinfo = {
> +static const TypeInfo virt_machine_typeinfo = {
>      .name       = MACHINE_TYPE_NAME("virt"),
>      .parent     = TYPE_MACHINE,
> -    .class_init = riscv_virt_machine_class_init,
> -    .instance_init = riscv_virt_machine_instance_init,
> +    .class_init = virt_machine_class_init,
> +    .instance_init = virt_machine_instance_init,
>      .instance_size = sizeof(RISCVVirtState),
>  };
>
> -static void riscv_virt_machine_init_register_types(void)
> +static void virt_machine_init_register_types(void)
>  {
> -    type_register_static(&riscv_virt_machine_typeinfo);
> +    type_register_static(&virt_machine_typeinfo);
>  }
>
> -type_init(riscv_virt_machine_init_register_types)
> +type_init(virt_machine_init_register_types)
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-05-26 17:01 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-21 14:42 [PATCH 1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions Bin Meng
2020-05-21 14:42 ` [PATCH 2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions Bin Meng
2020-05-21 14:48   ` Philippe Mathieu-Daudé
2020-05-26 16:50   ` Alistair Francis
2020-05-21 14:48 ` [PATCH 1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions Philippe Mathieu-Daudé
2020-05-21 22:09   ` Alistair Francis

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