QEMU-Devel Archive on lore.kernel.org
 help / color / Atom feed
From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Palmer Dabbelt <palmer@sifive.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v4 27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
Date: Thu, 22 Aug 2019 15:39:41 -0700
Message-ID: <CAKmqyKOYZvNsEtH4Vzja1qkSKJyBMCCS_iONdOP90EDjbq7EGg@mail.gmail.com> (raw)
In-Reply-To: <1566191521-7820-28-git-send-email-bmeng.cn@gmail.com>

On Sun, Aug 18, 2019 at 10:31 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> In the past we did not have a model for PRCI, hence two handcrafted
> clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the
> purpose of supplying hard-coded clock frequencies. But now since we
> have added the PRCI support in QEMU, we don't need them any more.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> ---
>
> Changes in v4:
> - new patch to remove handcrafted clock nodes for UART and ethernet
>
> Changes in v3: None
> Changes in v2: None
>
>  hw/riscv/sifive_u.c         | 24 +-----------------------
>  include/hw/riscv/sifive_u.h |  3 +--
>  2 files changed, 2 insertions(+), 25 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7a370e9..7d9fb3a 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -89,8 +89,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
>      uint32_t *cells;
>      char *nodename;
>      char ethclk_names[] = "pclk\0hclk";
> -    uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
> -    uint32_t uartclk_phandle;
> +    uint32_t plic_phandle, prci_phandle, phandle = 1;
>      uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
>
>      fdt = s->fdt = create_device_tree(&s->fdt_size);
> @@ -250,17 +249,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
>      g_free(cells);
>      g_free(nodename);
>
> -    ethclk_phandle = phandle++;
> -    nodename = g_strdup_printf("/soc/ethclk");
> -    qemu_fdt_add_subnode(fdt, nodename);
> -    qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
> -    qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
> -    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
> -        SIFIVE_U_GEM_CLOCK_FREQ);
> -    qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle);
> -    ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
> -    g_free(nodename);
> -
>      phy_phandle = phandle++;
>      nodename = g_strdup_printf("/soc/ethernet@%lx",
>          (long)memmap[SIFIVE_U_GEM].base);
> @@ -292,16 +280,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
>      qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
>      g_free(nodename);
>
> -    uartclk_phandle = phandle++;
> -    nodename = g_strdup_printf("/soc/uartclk");
> -    qemu_fdt_add_subnode(fdt, nodename);
> -    qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
> -    qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
> -    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
> -    qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle);
> -    uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
> -    g_free(nodename);
> -
>      nodename = g_strdup_printf("/soc/serial@%lx",
>          (long)memmap[SIFIVE_U_UART0].base);
>      qemu_fdt_add_subnode(fdt, nodename);
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index cba29e1..8880f9c 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -72,8 +72,7 @@ enum {
>  enum {
>      SIFIVE_U_CLOCK_FREQ = 1000000000,
>      SIFIVE_U_HFCLK_FREQ = 33333333,
> -    SIFIVE_U_RTCCLK_FREQ = 1000000,
> -    SIFIVE_U_GEM_CLOCK_FREQ = 125000000
> +    SIFIVE_U_RTCCLK_FREQ = 1000000
>  };
>
>  #define SIFIVE_U_MANAGEMENT_CPU_COUNT   1
> --
> 2.7.4
>
>


  reply index

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-19  5:11 [Qemu-devel] [PATCH v4 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 01/28] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 03/28] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 04/28] riscv: hw: Change create_fdt() to return void Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-08-19 20:08   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-08-22 22:40   ` Alistair Francis
2019-08-23  1:57     ` Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 15/28] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 16/28] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 17/28] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-08-19 20:21   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-08-19 20:22   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 19/28] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-08-20 18:26   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 21/28] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 22/28] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 23/28] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 24/28] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-08-22 22:41   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 25/28] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 26/28] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-08-19  5:12 ` [Qemu-devel] [PATCH v4 27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-08-22 22:39   ` Alistair Francis [this message]
2019-08-19  5:12 ` [Qemu-devel] [PATCH v4 28/28] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng

Reply instructions:

You may reply publically to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAKmqyKOYZvNsEtH4Vzja1qkSKJyBMCCS_iONdOP90EDjbq7EGg@mail.gmail.com \
    --to=alistair23@gmail.com \
    --cc="qemu-devel@nongnu.org \
    --cc=Alistair.Francis@wdc.com \
    --cc=bmeng.cn@gmail.com \
    --cc=palmer@sifive.com \
    --cc=qemu-riscv@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

QEMU-Devel Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/qemu-devel/0 qemu-devel/git/0.git
	git clone --mirror https://lore.kernel.org/qemu-devel/1 qemu-devel/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 qemu-devel qemu-devel/ https://lore.kernel.org/qemu-devel \
		qemu-devel@nongnu.org qemu-devel@archiver.kernel.org
	public-inbox-index qemu-devel

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.nongnu.qemu-devel


AGPL code for this site: git clone https://public-inbox.org/ public-inbox