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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=alistair23@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , Bin Meng , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Oct 15, 2021 at 5:50 PM wrote: > > From: Frank Chang > > TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in > commit: c445593, but other TB_FLAGS bits for rvv and rvh were > not shift as well so these bits may overlap with each other when > rvv is enabled. > > Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.h | 14 +++++++------- > target/riscv/translate.c | 2 +- > 2 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index d70f63ddfe6..d63a08b6e4c 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -380,7 +380,6 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, > target_ulong riscv_cpu_get_fflags(CPURISCVState *env); > void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); > > -#define TB_FLAGS_MMU_MASK 7 > #define TB_FLAGS_PRIV_MMU_MASK 3 > #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) > #define TB_FLAGS_MSTATUS_FS MSTATUS_FS > @@ -389,13 +388,14 @@ typedef CPURISCVState CPUArchState; > typedef RISCVCPU ArchCPU; > #include "exec/cpu-all.h" > > -FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) > -FIELD(TB_FLAGS, LMUL, 3, 2) > -FIELD(TB_FLAGS, SEW, 5, 3) > -FIELD(TB_FLAGS, VILL, 8, 1) > +FIELD(TB_FLAGS, MEM_IDX, 0, 3) > +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1) > +FIELD(TB_FLAGS, LMUL, 4, 2) > +FIELD(TB_FLAGS, SEW, 6, 3) > +FIELD(TB_FLAGS, VILL, 9, 1) > /* Is a Hypervisor instruction load/store allowed? */ > -FIELD(TB_FLAGS, HLSX, 9, 1) > -FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) > +FIELD(TB_FLAGS, HLSX, 10, 1) > +FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2) > > bool riscv_cpu_is_32bit(CPURISCVState *env); > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index f23bc919c08..a7a66cf9db1 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -544,7 +544,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > uint32_t tb_flags = ctx->base.tb->flags; > > ctx->pc_succ_insn = ctx->base.pc_first; > - ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK; > + ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); > ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; > ctx->priv_ver = env->priv_ver; > #if !defined(CONFIG_USER_ONLY) > -- > 2.25.1 > >