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That's all we know. X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , "open list:RISC-V" , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "qemu-devel@nongnu.org Developers" , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Aug 14, 2020 at 9:53 AM Bin Meng wrote: > > From: Bin Meng > > Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems > enough to create unimplemented devices to cover their register > spaces at this point. > > With this commit, QEMU can boot to U-Boot (2nd stage bootloader) > all the way to the Linux shell login prompt, with a modified HSS > (1st stage bootloader). > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > hw/riscv/microchip_pfsoc.c | 14 ++++++++++++++ > include/hw/riscv/microchip_pfsoc.h | 3 +++ > 2 files changed, 17 insertions(+) > > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 625b511..139284a 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -89,6 +89,9 @@ static const struct MemmapEntry { > [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, > [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, > [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, > + [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, > + [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, > + [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, > [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, > [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, > [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, > @@ -308,6 +311,17 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) > sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, > qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); > > + /* GPIOs */ > + create_unimplemented_device("microchip.pfsoc.gpio0", > + memmap[MICROCHIP_PFSOC_GPIO0].base, > + memmap[MICROCHIP_PFSOC_GPIO0].size); > + create_unimplemented_device("microchip.pfsoc.gpio1", > + memmap[MICROCHIP_PFSOC_GPIO1].base, > + memmap[MICROCHIP_PFSOC_GPIO1].size); > + create_unimplemented_device("microchip.pfsoc.gpio2", > + memmap[MICROCHIP_PFSOC_GPIO2].base, > + memmap[MICROCHIP_PFSOC_GPIO2].size); > + > /* eNVM */ > memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", > memmap[MICROCHIP_PFSOC_ENVM_DATA].size, > diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h > index 60f994c..993b17c 100644 > --- a/include/hw/riscv/microchip_pfsoc.h > +++ b/include/hw/riscv/microchip_pfsoc.h > @@ -89,6 +89,9 @@ enum { > MICROCHIP_PFSOC_MMUART4, > MICROCHIP_PFSOC_GEM0, > MICROCHIP_PFSOC_GEM1, > + MICROCHIP_PFSOC_GPIO0, > + MICROCHIP_PFSOC_GPIO1, > + MICROCHIP_PFSOC_GPIO2, > MICROCHIP_PFSOC_ENVM_CFG, > MICROCHIP_PFSOC_ENVM_DATA, > MICROCHIP_PFSOC_IOSCB_CFG, > -- > 2.7.4 > >