* [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
@ 2020-10-16 12:37 Ivan Griffin
2020-10-16 16:07 ` Alistair Francis
0 siblings, 1 reply; 12+ messages in thread
From: Ivan Griffin @ 2020-10-16 12:37 UTC (permalink / raw)
To: Bin Meng; +Cc: qemu-trivial, qemu-riscv, qemu-devel, ivan.griffin
Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
reporting a STORE/AMO Access Fault.
This region is used by the PolarFire SoC port of U-Boot to
interact with the FPGA system controller.
Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com>
---
hw/riscv/microchip_pfsoc.c | 6 ++++++
include/hw/riscv/microchip_pfsoc.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 4627179cd3..20e1496e3e 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -97,6 +97,7 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
+ [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 },
[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
[MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
};
@@ -341,6 +342,11 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
+
+ /* IOSCBCTRL */
+ create_unimplemented_device("microchip.pfsoc.ioscb.ctrl",
+ memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base,
+ memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size);
}
static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index 8bfc7e1a85..3f1874b162 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -95,6 +95,7 @@ enum {
MICROCHIP_PFSOC_ENVM_CFG,
MICROCHIP_PFSOC_ENVM_DATA,
MICROCHIP_PFSOC_IOSCB_CFG,
+ MICROCHIP_PFSOC_IOSCB_CTRL,
MICROCHIP_PFSOC_DRAM,
};
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
2020-10-16 12:37 [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry Ivan Griffin
@ 2020-10-16 16:07 ` Alistair Francis
2020-10-16 16:31 ` Ivan Griffin
0 siblings, 1 reply; 12+ messages in thread
From: Alistair Francis @ 2020-10-16 16:07 UTC (permalink / raw)
To: Ivan Griffin
Cc: QEMU Trivial, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Fri, Oct 16, 2020 at 8:04 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
>
> Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
> reporting a STORE/AMO Access Fault.
>
> This region is used by the PolarFire SoC port of U-Boot to
> interact with the FPGA system controller.
>
> Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com>
> ---
> hw/riscv/microchip_pfsoc.c | 6 ++++++
> include/hw/riscv/microchip_pfsoc.h | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 4627179cd3..20e1496e3e 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -97,6 +97,7 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> + [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 },
I don't see this in the UG0880 "User Guide PolarFire SoC FPGA
Microprocessor Sub-System" memory map.
Where is this documented?
Alistair
> [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
> [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
> };
> @@ -341,6 +342,11 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
> memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
> memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
> +
> + /* IOSCBCTRL */
> + create_unimplemented_device("microchip.pfsoc.ioscb.ctrl",
> + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base,
> + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size);
> }
>
> static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
> index 8bfc7e1a85..3f1874b162 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -95,6 +95,7 @@ enum {
> MICROCHIP_PFSOC_ENVM_CFG,
> MICROCHIP_PFSOC_ENVM_DATA,
> MICROCHIP_PFSOC_IOSCB_CFG,
> + MICROCHIP_PFSOC_IOSCB_CTRL,
> MICROCHIP_PFSOC_DRAM,
> };
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
2020-10-16 16:31 ` Ivan Griffin
@ 2020-10-16 16:24 ` Alistair Francis
2020-10-16 17:10 ` [PATCH v2] " Ivan Griffin
2020-10-19 2:05 ` [PATCH] " Bin Meng
1 sibling, 1 reply; 12+ messages in thread
From: Alistair Francis @ 2020-10-16 16:24 UTC (permalink / raw)
To: Ivan Griffin
Cc: QEMU Trivial, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Fri, Oct 16, 2020 at 9:31 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
>
> I don't know why it isn't documented in that PDF (or in the register map), but if you check https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.h you'll see the following
>
> ```
> typedef struct
> {
> volatile uint32_t SOFT_RESET;
> volatile uint32_t VDETECTOR;
> volatile uint32_t TVS_CONTROL;
> volatile uint32_t TVS_TEMP_A;
> volatile uint32_t TVS_TEMP_B;
> volatile uint32_t TVS_TEMP_C;
> volatile uint32_t TVS_VOLT_A;
> volatile uint32_t TVS_VOLT_B;
> volatile uint32_t TVS_VOLT_C;
> volatile uint32_t TVS_OUTPUT0;
> volatile uint32_t TVS_OUTPUT1;
> volatile uint32_t TVS_TRIGGER;
> volatile uint32_t TRIM_VDET1P05;
> volatile uint32_t TRIM_VDET1P8;
> volatile uint32_t TRIM_VDET2P5;
> volatile uint32_t TRIM_TVS;
> volatile uint32_t TRIM_GDET1P05;
> volatile uint32_t RESERVED0;
> volatile uint32_t RESERVED1;
> volatile uint32_t RESERVED2;
> volatile uint32_t SERVICES_CR;
> volatile uint32_t SERVICES_SR;
> volatile uint32_t USER_DETECTOR_SR;
> volatile uint32_t USER_DETECTOR_CR;
> volatile uint32_t MSS_SPI_CR;
>
> } SCBCTRL_TypeDef;
>
> #define MSS_SCBCTRL ((SCBCTRL_TypeDef*) (0x37020000UL))
>
> /*2kB bytes long mailbox.*/
> #define MSS_SCBMAILBOX ((uint32_t*) (0x37020800UL))
> ```
>
> And in https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.c you'll see MSS_SCB and MSS_SCBMAILBOX used in many places to interact with the FPGA system controller to perform various services.
Ok, so the memory map exists, but not documented in the official documentation.
In this case it's fine to add. Can you add a comment though saying
that it's not documented in the official documentation though?
Otherwise it will confuse developers.
Alistair
>
>
> Cheers,
> Ivan
>
>
> -----Original Message-----
> From: Alistair Francis <alistair23@gmail.com>
> Sent: Friday 16 October 2020 17:08
> To: Ivan Griffin <ivan.griffin@emdalo.com>
> Cc: Bin Meng <bin.meng@windriver.com>; QEMU Trivial <qemu-trivial@nongnu.org>; open list:RISC-V <qemu-riscv@nongnu.org>; qemu-devel@nongnu.org Developers <qemu-devel@nongnu.org>
> Subject: Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
>
> On Fri, Oct 16, 2020 at 8:04 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
> >
> > Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
> > reporting a STORE/AMO Access Fault.
> >
> > This region is used by the PolarFire SoC port of U-Boot to interact
> > with the FPGA system controller.
> >
> > Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com>
> > ---
> > hw/riscv/microchip_pfsoc.c | 6 ++++++
> > include/hw/riscv/microchip_pfsoc.h | 1 +
> > 2 files changed, 7 insertions(+)
> >
> > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> > index 4627179cd3..20e1496e3e 100644
> > --- a/hw/riscv/microchip_pfsoc.c
> > +++ b/hw/riscv/microchip_pfsoc.c
> > @@ -97,6 +97,7 @@ static const struct MemmapEntry {
> > [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
> > [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> > [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> > + [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 },
>
> I don't see this in the UG0880 "User Guide PolarFire SoC FPGA Microprocessor Sub-System" memory map.
>
> Where is this documented?
>
> Alistair
>
> > [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
> > [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
> > };
> > @@ -341,6 +342,11 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> > create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
> > memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
> > memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
> > +
> > + /* IOSCBCTRL */
> > + create_unimplemented_device("microchip.pfsoc.ioscb.ctrl",
> > + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base,
> > + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size);
> > }
> >
> > static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void
> > *data) diff --git a/include/hw/riscv/microchip_pfsoc.h
> > b/include/hw/riscv/microchip_pfsoc.h
> > index 8bfc7e1a85..3f1874b162 100644
> > --- a/include/hw/riscv/microchip_pfsoc.h
> > +++ b/include/hw/riscv/microchip_pfsoc.h
> > @@ -95,6 +95,7 @@ enum {
> > MICROCHIP_PFSOC_ENVM_CFG,
> > MICROCHIP_PFSOC_ENVM_DATA,
> > MICROCHIP_PFSOC_IOSCB_CFG,
> > + MICROCHIP_PFSOC_IOSCB_CTRL,
> > MICROCHIP_PFSOC_DRAM,
> > };
> >
> > --
> > 2.17.1
> >
> >
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
2020-10-16 16:07 ` Alistair Francis
@ 2020-10-16 16:31 ` Ivan Griffin
2020-10-16 16:24 ` Alistair Francis
2020-10-19 2:05 ` [PATCH] " Bin Meng
0 siblings, 2 replies; 12+ messages in thread
From: Ivan Griffin @ 2020-10-16 16:31 UTC (permalink / raw)
To: Alistair Francis
Cc: QEMU Trivial, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
I don't know why it isn't documented in that PDF (or in the register map), but if you check https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.h you'll see the following
```
typedef struct
{
volatile uint32_t SOFT_RESET;
volatile uint32_t VDETECTOR;
volatile uint32_t TVS_CONTROL;
volatile uint32_t TVS_TEMP_A;
volatile uint32_t TVS_TEMP_B;
volatile uint32_t TVS_TEMP_C;
volatile uint32_t TVS_VOLT_A;
volatile uint32_t TVS_VOLT_B;
volatile uint32_t TVS_VOLT_C;
volatile uint32_t TVS_OUTPUT0;
volatile uint32_t TVS_OUTPUT1;
volatile uint32_t TVS_TRIGGER;
volatile uint32_t TRIM_VDET1P05;
volatile uint32_t TRIM_VDET1P8;
volatile uint32_t TRIM_VDET2P5;
volatile uint32_t TRIM_TVS;
volatile uint32_t TRIM_GDET1P05;
volatile uint32_t RESERVED0;
volatile uint32_t RESERVED1;
volatile uint32_t RESERVED2;
volatile uint32_t SERVICES_CR;
volatile uint32_t SERVICES_SR;
volatile uint32_t USER_DETECTOR_SR;
volatile uint32_t USER_DETECTOR_CR;
volatile uint32_t MSS_SPI_CR;
} SCBCTRL_TypeDef;
#define MSS_SCBCTRL ((SCBCTRL_TypeDef*) (0x37020000UL))
/*2kB bytes long mailbox.*/
#define MSS_SCBMAILBOX ((uint32_t*) (0x37020800UL))
```
And in https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.c you'll see MSS_SCB and MSS_SCBMAILBOX used in many places to interact with the FPGA system controller to perform various services.
Cheers,
Ivan
-----Original Message-----
From: Alistair Francis <alistair23@gmail.com>
Sent: Friday 16 October 2020 17:08
To: Ivan Griffin <ivan.griffin@emdalo.com>
Cc: Bin Meng <bin.meng@windriver.com>; QEMU Trivial <qemu-trivial@nongnu.org>; open list:RISC-V <qemu-riscv@nongnu.org>; qemu-devel@nongnu.org Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
On Fri, Oct 16, 2020 at 8:04 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
>
> Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
> reporting a STORE/AMO Access Fault.
>
> This region is used by the PolarFire SoC port of U-Boot to interact
> with the FPGA system controller.
>
> Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com>
> ---
> hw/riscv/microchip_pfsoc.c | 6 ++++++
> include/hw/riscv/microchip_pfsoc.h | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 4627179cd3..20e1496e3e 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -97,6 +97,7 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> + [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 },
I don't see this in the UG0880 "User Guide PolarFire SoC FPGA Microprocessor Sub-System" memory map.
Where is this documented?
Alistair
> [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
> [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
> };
> @@ -341,6 +342,11 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
> memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
> memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
> +
> + /* IOSCBCTRL */
> + create_unimplemented_device("microchip.pfsoc.ioscb.ctrl",
> + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base,
> + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size);
> }
>
> static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void
> *data) diff --git a/include/hw/riscv/microchip_pfsoc.h
> b/include/hw/riscv/microchip_pfsoc.h
> index 8bfc7e1a85..3f1874b162 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -95,6 +95,7 @@ enum {
> MICROCHIP_PFSOC_ENVM_CFG,
> MICROCHIP_PFSOC_ENVM_DATA,
> MICROCHIP_PFSOC_IOSCB_CFG,
> + MICROCHIP_PFSOC_IOSCB_CTRL,
> MICROCHIP_PFSOC_DRAM,
> };
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
2020-10-16 16:24 ` Alistair Francis
@ 2020-10-16 17:10 ` Ivan Griffin
2020-10-16 17:37 ` Alistair Francis
2020-10-19 1:57 ` Bin Meng
0 siblings, 2 replies; 12+ messages in thread
From: Ivan Griffin @ 2020-10-16 17:10 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-trivial, qemu-riscv, qemu-devel, ivan.griffin
Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
reporting a STORE/AMO Access Fault.
This region is used by the PolarFire SoC port of U-Boot to
interact with the FPGA system controller.
Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com>
---
hw/riscv/microchip_pfsoc.c | 10 ++++++++++
include/hw/riscv/microchip_pfsoc.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 4627179cd3..9aaa276ee2 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -97,6 +97,7 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
+ [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 },
[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
[MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
};
@@ -341,6 +342,15 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
+
+ /* IOSCBCTRL
+ *
+ * These registers are not documented in the official documentation
+ * but used by the polarfire-soc-bare-meta-library code
+ */
+ create_unimplemented_device("microchip.pfsoc.ioscb.ctrl",
+ memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base,
+ memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size);
}
static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index 8bfc7e1a85..3f1874b162 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -95,6 +95,7 @@ enum {
MICROCHIP_PFSOC_ENVM_CFG,
MICROCHIP_PFSOC_ENVM_DATA,
MICROCHIP_PFSOC_IOSCB_CFG,
+ MICROCHIP_PFSOC_IOSCB_CTRL,
MICROCHIP_PFSOC_DRAM,
};
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
2020-10-16 17:10 ` [PATCH v2] " Ivan Griffin
@ 2020-10-16 17:37 ` Alistair Francis
2020-10-19 1:57 ` Bin Meng
1 sibling, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2020-10-16 17:37 UTC (permalink / raw)
To: Ivan Griffin
Cc: QEMU Trivial, open list:RISC-V, qemu-devel@nongnu.org Developers
On Fri, Oct 16, 2020 at 10:10 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
>
> Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
> reporting a STORE/AMO Access Fault.
>
> This region is used by the PolarFire SoC port of U-Boot to
> interact with the FPGA system controller.
>
> Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/microchip_pfsoc.c | 10 ++++++++++
> include/hw/riscv/microchip_pfsoc.h | 1 +
> 2 files changed, 11 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 4627179cd3..9aaa276ee2 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -97,6 +97,7 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> + [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 },
> [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
> [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
> };
> @@ -341,6 +342,15 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
> memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
> memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
> +
> + /* IOSCBCTRL
> + *
> + * These registers are not documented in the official documentation
> + * but used by the polarfire-soc-bare-meta-library code
> + */
> + create_unimplemented_device("microchip.pfsoc.ioscb.ctrl",
> + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base,
> + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size);
> }
>
> static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
> index 8bfc7e1a85..3f1874b162 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -95,6 +95,7 @@ enum {
> MICROCHIP_PFSOC_ENVM_CFG,
> MICROCHIP_PFSOC_ENVM_DATA,
> MICROCHIP_PFSOC_IOSCB_CFG,
> + MICROCHIP_PFSOC_IOSCB_CTRL,
> MICROCHIP_PFSOC_DRAM,
> };
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
2020-10-16 17:10 ` [PATCH v2] " Ivan Griffin
2020-10-16 17:37 ` Alistair Francis
@ 2020-10-19 1:57 ` Bin Meng
2020-10-27 20:56 ` Alistair Francis
1 sibling, 1 reply; 12+ messages in thread
From: Bin Meng @ 2020-10-19 1:57 UTC (permalink / raw)
To: Ivan Griffin
Cc: qemu-trivial, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers
Hi Ivan,
On Sat, Oct 17, 2020 at 1:10 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
>
> Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
> reporting a STORE/AMO Access Fault.
>
> This region is used by the PolarFire SoC port of U-Boot to
> interact with the FPGA system controller.
>
> Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com>
> ---
> hw/riscv/microchip_pfsoc.c | 10 ++++++++++
> include/hw/riscv/microchip_pfsoc.h | 1 +
> 2 files changed, 11 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 4627179cd3..9aaa276ee2 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -97,6 +97,7 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> + [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 },
> [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
> [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
> };
> @@ -341,6 +342,15 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
> memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
> memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
> +
> + /* IOSCBCTRL
> + *
> + * These registers are not documented in the official documentation
> + * but used by the polarfire-soc-bare-meta-library code
> + */
> + create_unimplemented_device("microchip.pfsoc.ioscb.ctrl",
> + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base,
> + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size);
> }
>
> static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
> index 8bfc7e1a85..3f1874b162 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -95,6 +95,7 @@ enum {
> MICROCHIP_PFSOC_ENVM_CFG,
> MICROCHIP_PFSOC_ENVM_DATA,
> MICROCHIP_PFSOC_IOSCB_CFG,
> + MICROCHIP_PFSOC_IOSCB_CTRL,
> MICROCHIP_PFSOC_DRAM,
> };
Thank you for the patch!
I am currently adding the DDR controller modeling support to PolarFire
SoC which will cover this memory map. With my patch series, your patch
is no longer needed.
Regards,
Bin
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
2020-10-16 16:31 ` Ivan Griffin
2020-10-16 16:24 ` Alistair Francis
@ 2020-10-19 2:05 ` Bin Meng
2020-10-19 8:17 ` Ivan Griffin
1 sibling, 1 reply; 12+ messages in thread
From: Bin Meng @ 2020-10-19 2:05 UTC (permalink / raw)
To: Ivan Griffin
Cc: QEMU Trivial, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
Hi Ivan,
On Sat, Oct 17, 2020 at 12:31 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
>
> I don't know why it isn't documented in that PDF (or in the register map), but if you check https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.h you'll see the following
>
> ```
> typedef struct
> {
> volatile uint32_t SOFT_RESET;
> volatile uint32_t VDETECTOR;
> volatile uint32_t TVS_CONTROL;
> volatile uint32_t TVS_TEMP_A;
> volatile uint32_t TVS_TEMP_B;
> volatile uint32_t TVS_TEMP_C;
> volatile uint32_t TVS_VOLT_A;
> volatile uint32_t TVS_VOLT_B;
> volatile uint32_t TVS_VOLT_C;
> volatile uint32_t TVS_OUTPUT0;
> volatile uint32_t TVS_OUTPUT1;
> volatile uint32_t TVS_TRIGGER;
> volatile uint32_t TRIM_VDET1P05;
> volatile uint32_t TRIM_VDET1P8;
> volatile uint32_t TRIM_VDET2P5;
> volatile uint32_t TRIM_TVS;
> volatile uint32_t TRIM_GDET1P05;
> volatile uint32_t RESERVED0;
> volatile uint32_t RESERVED1;
> volatile uint32_t RESERVED2;
> volatile uint32_t SERVICES_CR;
> volatile uint32_t SERVICES_SR;
> volatile uint32_t USER_DETECTOR_SR;
> volatile uint32_t USER_DETECTOR_CR;
> volatile uint32_t MSS_SPI_CR;
>
> } SCBCTRL_TypeDef;
>
> #define MSS_SCBCTRL ((SCBCTRL_TypeDef*) (0x37020000UL))
>
> /*2kB bytes long mailbox.*/
> #define MSS_SCBMAILBOX ((uint32_t*) (0x37020800UL))
> ```
>
> And in https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.c you'll see MSS_SCB and MSS_SCBMAILBOX used in many places to interact with the FPGA system controller to perform various services.
It's actually documented, but not in the PDF file. I also spent some
time locating the doc when I do the DDR controller modeling work.
See Register Map/PF_SoC_RegMap_V1_1/MPFS250T/pfsoc_control_scb.htm in
https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map
Regards,
Bin
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
2020-10-19 2:05 ` [PATCH] " Bin Meng
@ 2020-10-19 8:17 ` Ivan Griffin
2020-10-19 8:38 ` Bin Meng
0 siblings, 1 reply; 12+ messages in thread
From: Ivan Griffin @ 2020-10-19 8:17 UTC (permalink / raw)
To: Bin Meng
Cc: QEMU Trivial, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers
[-- Attachment #1: Type: text/plain, Size: 2783 bytes --]
Hi Bin,
Well spotted with the register map. I grepped it for 0x37020000 and didn't find it, but it seems the address (incorrectly) is 0x07020000 in the documentation.
Thanks,
Ivan.
________________________________
From: Bin Meng <bmeng.cn@gmail.com>
Sent: Monday 19 October 2020 03:05
To: Ivan Griffin <ivan.griffin@emdalo.com>
Cc: Alistair Francis <alistair23@gmail.com>; QEMU Trivial <qemu-trivial@nongnu.org>; Bin Meng <bin.meng@windriver.com>; open list:RISC-V <qemu-riscv@nongnu.org>; qemu-devel@nongnu.org Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
Hi Ivan,
On Sat, Oct 17, 2020 at 12:31 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
>
> I don't know why it isn't documented in that PDF (or in the register map), but if you check https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.h you'll see the following
>
> ```
> typedef struct
> {
> volatile uint32_t SOFT_RESET;
> volatile uint32_t VDETECTOR;
> volatile uint32_t TVS_CONTROL;
> volatile uint32_t TVS_TEMP_A;
> volatile uint32_t TVS_TEMP_B;
> volatile uint32_t TVS_TEMP_C;
> volatile uint32_t TVS_VOLT_A;
> volatile uint32_t TVS_VOLT_B;
> volatile uint32_t TVS_VOLT_C;
> volatile uint32_t TVS_OUTPUT0;
> volatile uint32_t TVS_OUTPUT1;
> volatile uint32_t TVS_TRIGGER;
> volatile uint32_t TRIM_VDET1P05;
> volatile uint32_t TRIM_VDET1P8;
> volatile uint32_t TRIM_VDET2P5;
> volatile uint32_t TRIM_TVS;
> volatile uint32_t TRIM_GDET1P05;
> volatile uint32_t RESERVED0;
> volatile uint32_t RESERVED1;
> volatile uint32_t RESERVED2;
> volatile uint32_t SERVICES_CR;
> volatile uint32_t SERVICES_SR;
> volatile uint32_t USER_DETECTOR_SR;
> volatile uint32_t USER_DETECTOR_CR;
> volatile uint32_t MSS_SPI_CR;
>
> } SCBCTRL_TypeDef;
>
> #define MSS_SCBCTRL ((SCBCTRL_TypeDef*) (0x37020000UL))
>
> /*2kB bytes long mailbox.*/
> #define MSS_SCBMAILBOX ((uint32_t*) (0x37020800UL))
> ```
>
> And in https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.c you'll see MSS_SCB and MSS_SCBMAILBOX used in many places to interact with the FPGA system controller to perform various services.
It's actually documented, but not in the PDF file. I also spent some
time locating the doc when I do the DDR controller modeling work.
See Register Map/PF_SoC_RegMap_V1_1/MPFS250T/pfsoc_control_scb.htm in
https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map
Regards,
Bin
[-- Attachment #2: Type: text/html, Size: 5735 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
2020-10-19 8:17 ` Ivan Griffin
@ 2020-10-19 8:38 ` Bin Meng
2020-10-19 8:42 ` Ivan Griffin
0 siblings, 1 reply; 12+ messages in thread
From: Bin Meng @ 2020-10-19 8:38 UTC (permalink / raw)
To: Ivan Griffin
Cc: QEMU Trivial, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers
Hi Ivan,
On Mon, Oct 19, 2020 at 4:17 PM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
>
> Hi Bin,
>
> Well spotted with the register map. I grepped it for 0x37020000 and didn't find it, but it seems the address (incorrectly) is 0x07020000 in the documentation.
>
I believe the documented offset 0x07020000 is the offset into the
IOSCB block, not the final one that is mapped into the system memory.
Regards,
Bin
> ________________________________
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: Monday 19 October 2020 03:05
> To: Ivan Griffin <ivan.griffin@emdalo.com>
> Cc: Alistair Francis <alistair23@gmail.com>; QEMU Trivial <qemu-trivial@nongnu.org>; Bin Meng <bin.meng@windriver.com>; open list:RISC-V <qemu-riscv@nongnu.org>; qemu-devel@nongnu.org Developers <qemu-devel@nongnu.org>
> Subject: Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
>
> Hi Ivan,
>
> On Sat, Oct 17, 2020 at 12:31 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
> >
> > I don't know why it isn't documented in that PDF (or in the register map), but if you check https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.h you'll see the following
> >
> > ```
> > typedef struct
> > {
> > volatile uint32_t SOFT_RESET;
> > volatile uint32_t VDETECTOR;
> > volatile uint32_t TVS_CONTROL;
> > volatile uint32_t TVS_TEMP_A;
> > volatile uint32_t TVS_TEMP_B;
> > volatile uint32_t TVS_TEMP_C;
> > volatile uint32_t TVS_VOLT_A;
> > volatile uint32_t TVS_VOLT_B;
> > volatile uint32_t TVS_VOLT_C;
> > volatile uint32_t TVS_OUTPUT0;
> > volatile uint32_t TVS_OUTPUT1;
> > volatile uint32_t TVS_TRIGGER;
> > volatile uint32_t TRIM_VDET1P05;
> > volatile uint32_t TRIM_VDET1P8;
> > volatile uint32_t TRIM_VDET2P5;
> > volatile uint32_t TRIM_TVS;
> > volatile uint32_t TRIM_GDET1P05;
> > volatile uint32_t RESERVED0;
> > volatile uint32_t RESERVED1;
> > volatile uint32_t RESERVED2;
> > volatile uint32_t SERVICES_CR;
> > volatile uint32_t SERVICES_SR;
> > volatile uint32_t USER_DETECTOR_SR;
> > volatile uint32_t USER_DETECTOR_CR;
> > volatile uint32_t MSS_SPI_CR;
> >
> > } SCBCTRL_TypeDef;
> >
> > #define MSS_SCBCTRL ((SCBCTRL_TypeDef*) (0x37020000UL))
> >
> > /*2kB bytes long mailbox.*/
> > #define MSS_SCBMAILBOX ((uint32_t*) (0x37020800UL))
> > ```
> >
> > And in https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.c you'll see MSS_SCB and MSS_SCBMAILBOX used in many places to interact with the FPGA system controller to perform various services.
>
> It's actually documented, but not in the PDF file. I also spent some
> time locating the doc when I do the DDR controller modeling work.
>
> See Register Map/PF_SoC_RegMap_V1_1/MPFS250T/pfsoc_control_scb.htm in
> https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
2020-10-19 8:38 ` Bin Meng
@ 2020-10-19 8:42 ` Ivan Griffin
0 siblings, 0 replies; 12+ messages in thread
From: Ivan Griffin @ 2020-10-19 8:42 UTC (permalink / raw)
To: Bin Meng
Cc: QEMU Trivial, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers
[-- Attachment #1: Type: text/plain, Size: 3779 bytes --]
Yes, it could be.
But the "Physical Address" column, in my mind, should be the 0x37020000 address. At least when I check other peripherals, their physical address values in the register map HTML corresponds to the source code.
Cheers,
Ivan.
________________________________
From: Bin Meng <bmeng.cn@gmail.com>
Sent: Monday 19 October 2020 09:38
To: Ivan Griffin <ivan.griffin@emdalo.com>
Cc: Alistair Francis <alistair23@gmail.com>; QEMU Trivial <qemu-trivial@nongnu.org>; open list:RISC-V <qemu-riscv@nongnu.org>; qemu-devel@nongnu.org Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
Hi Ivan,
On Mon, Oct 19, 2020 at 4:17 PM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
>
> Hi Bin,
>
> Well spotted with the register map. I grepped it for 0x37020000 and didn't find it, but it seems the address (incorrectly) is 0x07020000 in the documentation.
>
I believe the documented offset 0x07020000 is the offset into the
IOSCB block, not the final one that is mapped into the system memory.
Regards,
Bin
> ________________________________
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: Monday 19 October 2020 03:05
> To: Ivan Griffin <ivan.griffin@emdalo.com>
> Cc: Alistair Francis <alistair23@gmail.com>; QEMU Trivial <qemu-trivial@nongnu.org>; Bin Meng <bin.meng@windriver.com>; open list:RISC-V <qemu-riscv@nongnu.org>; qemu-devel@nongnu.org Developers <qemu-devel@nongnu.org>
> Subject: Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
>
> Hi Ivan,
>
> On Sat, Oct 17, 2020 at 12:31 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
> >
> > I don't know why it isn't documented in that PDF (or in the register map), but if you check https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.h you'll see the following
> >
> > ```
> > typedef struct
> > {
> > volatile uint32_t SOFT_RESET;
> > volatile uint32_t VDETECTOR;
> > volatile uint32_t TVS_CONTROL;
> > volatile uint32_t TVS_TEMP_A;
> > volatile uint32_t TVS_TEMP_B;
> > volatile uint32_t TVS_TEMP_C;
> > volatile uint32_t TVS_VOLT_A;
> > volatile uint32_t TVS_VOLT_B;
> > volatile uint32_t TVS_VOLT_C;
> > volatile uint32_t TVS_OUTPUT0;
> > volatile uint32_t TVS_OUTPUT1;
> > volatile uint32_t TVS_TRIGGER;
> > volatile uint32_t TRIM_VDET1P05;
> > volatile uint32_t TRIM_VDET1P8;
> > volatile uint32_t TRIM_VDET2P5;
> > volatile uint32_t TRIM_TVS;
> > volatile uint32_t TRIM_GDET1P05;
> > volatile uint32_t RESERVED0;
> > volatile uint32_t RESERVED1;
> > volatile uint32_t RESERVED2;
> > volatile uint32_t SERVICES_CR;
> > volatile uint32_t SERVICES_SR;
> > volatile uint32_t USER_DETECTOR_SR;
> > volatile uint32_t USER_DETECTOR_CR;
> > volatile uint32_t MSS_SPI_CR;
> >
> > } SCBCTRL_TypeDef;
> >
> > #define MSS_SCBCTRL ((SCBCTRL_TypeDef*) (0x37020000UL))
> >
> > /*2kB bytes long mailbox.*/
> > #define MSS_SCBMAILBOX ((uint32_t*) (0x37020800UL))
> > ```
> >
> > And in https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.c you'll see MSS_SCB and MSS_SCBMAILBOX used in many places to interact with the FPGA system controller to perform various services.
>
> It's actually documented, but not in the PDF file. I also spent some
> time locating the doc when I do the DDR controller modeling work.
>
> See Register Map/PF_SoC_RegMap_V1_1/MPFS250T/pfsoc_control_scb.htm in
> https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map
[-- Attachment #2: Type: text/html, Size: 7203 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
2020-10-19 1:57 ` Bin Meng
@ 2020-10-27 20:56 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2020-10-27 20:56 UTC (permalink / raw)
To: Bin Meng
Cc: QEMU Trivial, open list:RISC-V, qemu-devel@nongnu.org Developers,
Ivan Griffin
On Sun, Oct 18, 2020 at 6:58 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Ivan,
>
> On Sat, Oct 17, 2020 at 1:10 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
> >
> > Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
> > reporting a STORE/AMO Access Fault.
> >
> > This region is used by the PolarFire SoC port of U-Boot to
> > interact with the FPGA system controller.
> >
> > Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com>
> > ---
> > hw/riscv/microchip_pfsoc.c | 10 ++++++++++
> > include/hw/riscv/microchip_pfsoc.h | 1 +
> > 2 files changed, 11 insertions(+)
> >
> > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> > index 4627179cd3..9aaa276ee2 100644
> > --- a/hw/riscv/microchip_pfsoc.c
> > +++ b/hw/riscv/microchip_pfsoc.c
> > @@ -97,6 +97,7 @@ static const struct MemmapEntry {
> > [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
> > [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> > [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> > + [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 },
> > [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
> > [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
> > };
> > @@ -341,6 +342,15 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> > create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
> > memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
> > memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
> > +
> > + /* IOSCBCTRL
> > + *
> > + * These registers are not documented in the official documentation
> > + * but used by the polarfire-soc-bare-meta-library code
> > + */
> > + create_unimplemented_device("microchip.pfsoc.ioscb.ctrl",
> > + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base,
> > + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size);
> > }
> >
> > static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
> > diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
> > index 8bfc7e1a85..3f1874b162 100644
> > --- a/include/hw/riscv/microchip_pfsoc.h
> > +++ b/include/hw/riscv/microchip_pfsoc.h
> > @@ -95,6 +95,7 @@ enum {
> > MICROCHIP_PFSOC_ENVM_CFG,
> > MICROCHIP_PFSOC_ENVM_DATA,
> > MICROCHIP_PFSOC_IOSCB_CFG,
> > + MICROCHIP_PFSOC_IOSCB_CTRL,
> > MICROCHIP_PFSOC_DRAM,
> > };
>
> Thank you for the patch!
>
> I am currently adding the DDR controller modeling support to PolarFire
> SoC which will cover this memory map. With my patch series, your patch
> is no longer needed.
I forgot to apply this, and Bin just sent his series. So if it's ok
with you Ivan I'm just going to apply Bin's series instead. Sorry
about that.
Alistair
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-10-27 21:10 UTC | newest]
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2020-10-16 12:37 [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry Ivan Griffin
2020-10-16 16:07 ` Alistair Francis
2020-10-16 16:31 ` Ivan Griffin
2020-10-16 16:24 ` Alistair Francis
2020-10-16 17:10 ` [PATCH v2] " Ivan Griffin
2020-10-16 17:37 ` Alistair Francis
2020-10-19 1:57 ` Bin Meng
2020-10-27 20:56 ` Alistair Francis
2020-10-19 2:05 ` [PATCH] " Bin Meng
2020-10-19 8:17 ` Ivan Griffin
2020-10-19 8:38 ` Bin Meng
2020-10-19 8:42 ` Ivan Griffin
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