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Wed, 14 Apr 2021 15:34:16 -0700 (PDT) MIME-Version: 1.0 References: <20210412065246.1853-1-jiangyifei@huawei.com> <20210412065246.1853-10-jiangyifei@huawei.com> In-Reply-To: <20210412065246.1853-10-jiangyifei@huawei.com> From: Alistair Francis Date: Thu, 15 Apr 2021 08:33:50 +1000 Message-ID: Subject: Re: [PATCH RFC v5 09/12] target/riscv: Add host cpu type To: Yifei Jiang Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::131; envelope-from=alistair23@gmail.com; helo=mail-il1-x131.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm-riscv@lists.infradead.org, Anup Patel , "open list:RISC-V" , "open list:Overall" , Sagar Karandikar , libvir-list@redhat.com, Bastian Koppelmann , Bin Meng , "qemu-devel@nongnu.org Developers" , Alistair Francis , yinyipeng , Palmer Dabbelt , fanliang@huawei.com, "Wubin \(H\)" , Zhanghailiang Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Apr 12, 2021 at 4:54 PM Yifei Jiang wrote: > > 'host' type cpu is set isa to RVXLEN simply, more isa info > will obtain from KVM in kvm_arch_init_vcpu() > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 9 +++++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 10 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index dd34ab4978..8132d35a92 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -216,6 +216,12 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > } > #endif > > +static void riscv_host_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RVXLEN); > +} > + > static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) > { > ObjectClass *oc; > @@ -706,6 +712,9 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .class_init = riscv_cpu_class_init, > }, > DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), > +#if defined(CONFIG_KVM) > + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), > +#endif > #if defined(TARGET_RISCV32) > DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index a489d94187..3ca3dad341 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -43,6 +43,7 @@ > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") > +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > > #if defined(TARGET_RISCV32) > # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 > -- > 2.19.1 > >