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Thu, 20 May 2021 00:11:54 -0700 (PDT) MIME-Version: 1.0 References: <20210505160620.15723-1-frank.chang@sifive.com> <20210505160620.15723-12-frank.chang@sifive.com> In-Reply-To: <20210505160620.15723-12-frank.chang@sifive.com> From: Alistair Francis Date: Thu, 20 May 2021 17:11:27 +1000 Message-ID: Subject: Re: [PATCH v6 11/17] target/riscv: rvb: rotate (left/right) To: Frank Chang Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::12e; envelope-from=alistair23@gmail.com; helo=mail-il1-x12e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Bin Meng , Richard Henderson , "qemu-devel@nongnu.org Developers" , Alistair Francis , Palmer Dabbelt , Kito Cheng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, May 6, 2021 at 2:17 AM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn32.decode | 6 ++++ > target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++++++++++++++++ > target/riscv/translate.c | 36 +++++++++++++++++++++++ > 3 files changed, 81 insertions(+) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 6bc9bbae9e0..71a9a182c01 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -682,6 +682,8 @@ binv 0110100 .......... 001 ..... 0110011 @r > bext 0100100 .......... 101 ..... 0110011 @r > slo 0010000 .......... 001 ..... 0110011 @r > sro 0010000 .......... 101 ..... 0110011 @r > +ror 0110000 .......... 101 ..... 0110011 @r > +rol 0110000 .......... 001 ..... 0110011 @r > > bseti 00101. ........... 001 ..... 0010011 @sh > bclri 01001. ........... 001 ..... 0010011 @sh > @@ -689,6 +691,7 @@ binvi 01101. ........... 001 ..... 0010011 @sh > bexti 01001. ........... 101 ..... 0010011 @sh > sloi 00100. ........... 001 ..... 0010011 @sh > sroi 00100. ........... 101 ..... 0010011 @sh > +rori 01100. ........... 101 ..... 0010011 @sh > > # *** RV64B Standard Extension (in addition to RV32B) *** > clzw 0110000 00000 ..... 001 ..... 0011011 @r2 > @@ -703,9 +706,12 @@ binvw 0110100 .......... 001 ..... 0111011 @r > bextw 0100100 .......... 101 ..... 0111011 @r > slow 0010000 .......... 001 ..... 0111011 @r > srow 0010000 .......... 101 ..... 0111011 @r > +rorw 0110000 .......... 101 ..... 0111011 @r > +rolw 0110000 .......... 001 ..... 0111011 @r > > bsetiw 0010100 .......... 001 ..... 0011011 @sh5 > bclriw 0100100 .......... 001 ..... 0011011 @sh5 > binviw 0110100 .......... 001 ..... 0011011 @sh5 > sloiw 0010000 .......... 001 ..... 0011011 @sh5 > sroiw 0010000 .......... 101 ..... 0011011 @sh5 > +roriw 0110000 .......... 101 ..... 0011011 @sh5 > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc > index 28640322c43..429738db155 100644 > --- a/target/riscv/insn_trans/trans_rvb.c.inc > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -179,6 +179,24 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a) > return gen_shifti(ctx, a, gen_sro); > } > > +static bool trans_ror(DisasContext *ctx, arg_ror *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_shift(ctx, a, tcg_gen_rotr_tl); > +} > + > +static bool trans_rori(DisasContext *ctx, arg_rori *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_shifti(ctx, a, tcg_gen_rotr_tl); > +} > + > +static bool trans_rol(DisasContext *ctx, arg_rol *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_shift(ctx, a, tcg_gen_rotl_tl); > +} > + > static bool trans_clzw(DisasContext *ctx, arg_clzw *a) > { > REQUIRE_64BIT(ctx); > @@ -290,3 +308,24 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) > REQUIRE_EXT(ctx, RVB); > return gen_shiftiw(ctx, a, gen_sro); > } > + > +static bool trans_rorw(DisasContext *ctx, arg_rorw *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_EXT(ctx, RVB); > + return gen_shiftw(ctx, a, gen_rorw); > +} > + > +static bool trans_roriw(DisasContext *ctx, arg_roriw *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_EXT(ctx, RVB); > + return gen_shiftiw(ctx, a, gen_rorw); > +} > + > +static bool trans_rolw(DisasContext *ctx, arg_rolw *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_EXT(ctx, RVB); > + return gen_shiftw(ctx, a, gen_rolw); > +} > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 088cf9f7678..c09b93f1b8a 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -663,6 +663,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) > tcg_temp_free(t); > } > > +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) > +{ > + TCGv_i32 t1 = tcg_temp_new_i32(); > + TCGv_i32 t2 = tcg_temp_new_i32(); > + > + /* truncate to 32-bits */ > + tcg_gen_trunc_tl_i32(t1, arg1); > + tcg_gen_trunc_tl_i32(t2, arg2); > + > + tcg_gen_rotr_i32(t1, t1, t2); > + > + /* sign-extend 64-bits */ > + tcg_gen_ext_i32_tl(ret, t1); > + > + tcg_temp_free_i32(t1); > + tcg_temp_free_i32(t2); > +} > + > +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) > +{ > + TCGv_i32 t1 = tcg_temp_new_i32(); > + TCGv_i32 t2 = tcg_temp_new_i32(); > + > + /* truncate to 32-bits */ > + tcg_gen_trunc_tl_i32(t1, arg1); > + tcg_gen_trunc_tl_i32(t2, arg2); > + > + tcg_gen_rotl_i32(t1, t1, t2); > + > + /* sign-extend 64-bits */ > + tcg_gen_ext_i32_tl(ret, t1); > + > + tcg_temp_free_i32(t1); > + tcg_temp_free_i32(t2); > +} > + > static bool gen_arith(DisasContext *ctx, arg_r *a, > void(*func)(TCGv, TCGv, TCGv)) > { > -- > 2.17.1 > >