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X-Received-From: 2607:f8b0:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "arikalo@wavecomp.com" , Qemu Devel , Mikhail Abakumov , "amarkovic@wavecomp.com" , "philmd@redhat.com" , "aurelien@aurel32.net" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000fc978c05946645c8 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Monday, October 7, 2019, Alex Benn=C3=A9e wrote= : > > Mikhail Abakumov writes: > > > From: Mikhail Abakumov > > Hmm the email got truncated here. > > > > > This patch add xml files with gdb registers for mips. > > > > Signed-off-by: Mikhail Abakumov > > --- > > configure | 3 ++ > > gdb-xml/mips-core.xml | 84 +++++++++++++++++++++++++++++++++++++++++ > > gdb-xml/mips64-core.xml | 84 > > +++++++++++++++++++++++++++++++++++++++++ > > Otherwise for the configure/xml: > > Acked-by: Alex Benn=C3=A9e > > I assume the changes will go in via a MIPS tree. > > Yes, this should go via mips tree. Thanks for taking a look. Mikhail, thanks for this effort. Is there any way to include MSA registers, possibly in a separate file, and in a separate patch? What about a separate file for FPU registers? Can you take a look at corresponding solutions for other architectures? Yours, Aleksandar > > target/mips/cpu.c | 11 ++++++ > > 4 files changed, 182 insertions(+) > > create mode 100644 gdb-xml/mips-core.xml > > create mode 100644 gdb-xml/mips64-core.xml > > > > diff --git a/configure b/configure > > index 8f8446f52b..5bb2c62194 100755 > > --- a/configure > > +++ b/configure > > @@ -7466,12 +7466,14 @@ case "$target_name" in > > mips|mipsel) > > mttcg=3D"yes" > > TARGET_ARCH=3Dmips > > + gdb_xml_files=3D"mips-core.xml" > > echo "TARGET_ABI_MIPSO32=3Dy" >> $config_target_mak > > ;; > > mipsn32|mipsn32el) > > mttcg=3D"yes" > > TARGET_ARCH=3Dmips64 > > TARGET_BASE_ARCH=3Dmips > > + gdb_xml_files=3D"mips64-core.xml" > > echo "TARGET_ABI_MIPSN32=3Dy" >> $config_target_mak > > echo "TARGET_ABI32=3Dy" >> $config_target_mak > > ;; > > @@ -7479,6 +7481,7 @@ case "$target_name" in > > mttcg=3D"yes" > > TARGET_ARCH=3Dmips64 > > TARGET_BASE_ARCH=3Dmips > > + gdb_xml_files=3D"mips64-core.xml" > > echo "TARGET_ABI_MIPSN64=3Dy" >> $config_target_mak > > ;; > > moxie) > > diff --git a/gdb-xml/mips-core.xml b/gdb-xml/mips-core.xml > > new file mode 100644 > > index 0000000000..a46b2993eb > > --- /dev/null > > +++ b/gdb-xml/mips-core.xml > > @@ -0,0 +1,84 @@ > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > diff --git a/gdb-xml/mips64-core.xml b/gdb-xml/mips64-core.xml > > new file mode 100644 > > index 0000000000..cc1a15ad56 > > --- /dev/null > > +++ b/gdb-xml/mips64-core.xml > > @@ -0,0 +1,84 @@ > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > + > > diff --git a/target/mips/cpu.c b/target/mips/cpu.c > > index bbcf7ca463..014f1db59e 100644 > > --- a/target/mips/cpu.c > > +++ b/target/mips/cpu.c > > @@ -181,6 +181,11 @@ static ObjectClass *mips_cpu_class_by_name(const > > char *cpu_model) > > return oc; > > } > > > > +static gchar *mips_gdb_arch_name(CPUState *cs) > > +{ > > + return g_strdup("mips"); > > +} > > + > > static void mips_cpu_class_init(ObjectClass *c, void *data) > > { > > MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(c); > > @@ -213,6 +218,12 @@ static void mips_cpu_class_init(ObjectClass *c, > > void *data) > > cc->tlb_fill =3D mips_cpu_tlb_fill; > > #endif > > > > + cc->gdb_arch_name =3D mips_gdb_arch_name; > > +#ifdef TARGET_MIPS64 > > + cc->gdb_core_xml_file =3D "mips64-core.xml"; > > +#else > > + cc->gdb_core_xml_file =3D "mips-core.xml"; > > +#endif > > cc->gdb_num_core_regs =3D 73; > > cc->gdb_stop_before_watchpoint =3D true; > > } > > > -- > Alex Benn=C3=A9e > > --000000000000fc978c05946645c8 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Monday, October 7, 2019, Alex Benn=C3=A9e <alex.bennee@linaro.org> wrote:

Mikhail Abakumov <mikhail.= abakumov@ispras.ru> writes:

> From: Mikhail Abakumov <mikhail.abakumov@ispras>

Hmm the email got truncated here.

>
> This patch add xml files with gdb registers for mips.
>
> Signed-off-by: Mikhail Abakumov <mikhail.abakumov@ispras>
> ---
>=C2=A0 configure=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= |=C2=A0 3 ++
>=C2=A0 gdb-xml/mips-core.xml=C2=A0 =C2=A0| 84 +++++++++++++++++++++++++= ++++++++++++++++
>=C2=A0 gdb-xml/mips64-core.xml | 84
> +++++++++++++++++++++++++++++++++++++++++

Otherwise for the configure/xml:

Acked-by: Alex Benn=C3=A9e <al= ex.bennee@linaro.org>

I assume the changes will go in via a MIPS tree.


Yes, this should go via mips tree. Tha= nks for taking a look.


Mikhail, tha= nks for this effort.

Is there any way to include M= SA registers, possibly in a separate file, and in a separate patch? What ab= out a separate file for FPU registers? Can you take a look at corresponding= solutions for other architectures?

Yours,
Aleksandar


=C2=A0
>=C2=A0 target/mips/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0| 11 ++++++
>=C2=A0 4 files changed, 182 insertions(+)
>=C2=A0 create mode 100644 gdb-xml/mips-core.xml
>=C2=A0 create mode 100644 gdb-xml/mips64-core.xml
>
> diff --git a/configure b/configure
> index 8f8446f52b..5bb2c62194 100755
> --- a/configure
> +++ b/configure
> @@ -7466,12 +7466,14 @@ case "$target_name" in
>=C2=A0 =C2=A0 mips|mipsel)
>=C2=A0 =C2=A0 =C2=A0 mttcg=3D"yes"
>=C2=A0 =C2=A0 =C2=A0 TARGET_ARCH=3Dmips
> +=C2=A0 =C2=A0 gdb_xml_files=3D"mips-core.xml"
>=C2=A0 =C2=A0 =C2=A0 echo "TARGET_ABI_MIPSO32=3Dy" >> $= config_target_mak
>=C2=A0 =C2=A0 ;;
>=C2=A0 =C2=A0 mipsn32|mipsn32el)
>=C2=A0 =C2=A0 =C2=A0 mttcg=3D"yes"
>=C2=A0 =C2=A0 =C2=A0 TARGET_ARCH=3Dmips64
>=C2=A0 =C2=A0 =C2=A0 TARGET_BASE_ARCH=3Dmips
> +=C2=A0 =C2=A0 gdb_xml_files=3D"mips64-core.xml"
>=C2=A0 =C2=A0 =C2=A0 echo "TARGET_ABI_MIPSN32=3Dy" >> $= config_target_mak
>=C2=A0 =C2=A0 =C2=A0 echo "TARGET_ABI32=3Dy" >> $config= _target_mak
>=C2=A0 =C2=A0 ;;
> @@ -7479,6 +7481,7 @@ case "$target_name" in
>=C2=A0 =C2=A0 =C2=A0 mttcg=3D"yes"
>=C2=A0 =C2=A0 =C2=A0 TARGET_ARCH=3Dmips64
>=C2=A0 =C2=A0 =C2=A0 TARGET_BASE_ARCH=3Dmips
> +=C2=A0 =C2=A0 gdb_xml_files=3D"mips64-core.xml"
>=C2=A0 =C2=A0 =C2=A0 echo "TARGET_ABI_MIPSN64=3Dy" >> $= config_target_mak
>=C2=A0 =C2=A0 ;;
>=C2=A0 =C2=A0 moxie)
> diff --git a/gdb-xml/mips-core.xml b/gdb-xml/mips-core.xml
> new file mode 100644
> index 0000000000..a46b2993eb
> --- /dev/null
> +++ b/gdb-xml/mips-core.xml
> @@ -0,0 +1,84 @@
> +<?xml version=3D"1.0"?>
> +<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc.
> +
> +=C2=A0 =C2=A0 =C2=A0Copying and distribution of this file, with or wi= thout
> modification,
> +=C2=A0 =C2=A0 =C2=A0are permitted in any medium without royalty provi= ded the copyright
> +=C2=A0 =C2=A0 =C2=A0notice and this notice are preserved.=C2=A0 -->= ;
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name=3D"org.gnu.gdb.mips">
> +=C2=A0 <reg name=3D"zero" bitsize=3D"32"/><= br> > +=C2=A0 <reg name=3D"at" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"v0" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"v1" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"a0" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"a1" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"a2" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"a3" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"t0" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"t1" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"t2" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"t3" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"t4" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"t5" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"t6" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"t7" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"s0" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"s1" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"s2" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"s3" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"s4" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"s5" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"s6" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"s7" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"t8" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"t9" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"k0" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"k1" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"gp" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"sp" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"s8" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"ra" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"sr" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"lo" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"hi" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"bad" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"cause" bitsize=3D"32"/>=
> +=C2=A0 <reg name=3D"pc" bitsize=3D"32"/> > +
> +=C2=A0 <reg name=3D"f0" bitsize=3D"32" regnum= =3D"38"/>
> +=C2=A0 <reg name=3D"f1" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f2" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f3" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f4" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f5" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f6" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f7" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f8" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f9" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f10" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f11" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f12" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f13" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f14" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f15" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f16" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f17" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f18" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f19" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f20" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f21" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f22" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f23" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f24" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f25" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f26" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f27" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f28" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f29" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f30" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"f31" bitsize=3D"32"/> > +=C2=A0 <reg name=3D"fsr" bitsize=3D"32" group= =3D"float"/>
> +=C2=A0 <reg name=3D"fir" bitsize=3D"32" group= =3D"float"/>
> +=C2=A0 <reg name=3D"fp" bitsize=3D"32" group= =3D"float"/>
> +</feature>
> diff --git a/gdb-xml/mips64-core.xml b/gdb-xml/mips64-core.xml
> new file mode 100644
> index 0000000000..cc1a15ad56
> --- /dev/null
> +++ b/gdb-xml/mips64-core.xml
> @@ -0,0 +1,84 @@
> +<?xml version=3D"1.0"?>
> +<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc.
> +
> +=C2=A0 =C2=A0 =C2=A0Copying and distribution of this file, with or wi= thout
> modification,
> +=C2=A0 =C2=A0 =C2=A0are permitted in any medium without royalty provi= ded the copyright
> +=C2=A0 =C2=A0 =C2=A0notice and this notice are preserved.=C2=A0 -->= ;
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name=3D"org.gnu.gdb.mips64">
> +=C2=A0 <reg name=3D"zero" bitsize=3D"64"/><= br> > +=C2=A0 <reg name=3D"at" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"v0" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"v1" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"a0" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"a1" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"a2" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"a3" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"t0" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"t1" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"t2" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"t3" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"t4" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"t5" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"t6" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"t7" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"s0" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"s1" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"s2" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"s3" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"s4" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"s5" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"s6" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"s7" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"t8" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"t9" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"k0" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"k1" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"gp" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"sp" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"s8" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"ra" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"sr" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"lo" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"hi" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"bad" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"cause" bitsize=3D"64"/>=
> +=C2=A0 <reg name=3D"pc" bitsize=3D"64"/> > +
> +=C2=A0 <reg name=3D"f0" bitsize=3D"64" regnum= =3D"38"/>
> +=C2=A0 <reg name=3D"f1" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f2" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f3" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f4" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f5" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f6" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f7" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f8" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f9" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f10" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f11" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f12" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f13" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f14" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f15" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f16" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f17" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f18" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f19" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f20" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f21" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f22" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f23" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f24" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f25" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f26" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f27" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f28" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f29" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f30" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"f31" bitsize=3D"64"/> > +=C2=A0 <reg name=3D"fsr" bitsize=3D"64" group= =3D"float"/>
> +=C2=A0 <reg name=3D"fir" bitsize=3D"64" group= =3D"float"/>
> +=C2=A0 <reg name=3D"fp" bitsize=3D"64" group= =3D"float"/>
> +</feature>
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index bbcf7ca463..014f1db59e 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -181,6 +181,11 @@ static ObjectClass *mips_cpu_class_by_name(const<= br> > char *cpu_model)
>=C2=A0 =C2=A0 =C2=A0 return oc;
>=C2=A0 }
>
> +static gchar *mips_gdb_arch_name(CPUState *cs)
> +{
> +=C2=A0 =C2=A0 return g_strdup("mips");
> +}
> +
>=C2=A0 static void mips_cpu_class_init(ObjectClass *c, void *data)=
>=C2=A0 {
>=C2=A0 =C2=A0 =C2=A0 MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(c);
> @@ -213,6 +218,12 @@ static void mips_cpu_class_init(ObjectClass = *c,
> void *data)
>=C2=A0 =C2=A0 =C2=A0 cc->tlb_fill =3D mips_cpu_tlb_fill;
>=C2=A0 #endif
>
> +=C2=A0 =C2=A0 cc->gdb_arch_name =3D mips_gdb_arch_name;
> +#ifdef TARGET_MIPS64
> +=C2=A0 =C2=A0 cc->gdb_core_xml_file =3D "mips64-core.xml"= ;;
> +#else
> +=C2=A0 =C2=A0 cc->gdb_core_xml_file =3D "mips-core.xml";=
> +#endif
>=C2=A0 =C2=A0 =C2=A0 cc->gdb_num_core_regs =3D 73;
>=C2=A0 =C2=A0 =C2=A0 cc->gdb_stop_before_watchpoint =3D true;
>=C2=A0 }


--
Alex Benn=C3=A9e

--000000000000fc978c05946645c8--