QEMU-Devel Archive on lore.kernel.org
 help / color / Atom feed
From: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: "thuth@redhat.com" <thuth@redhat.com>,
	"Michael Rolnik" <mrolnik@gmail.com>,
	"richard.henderson@linaro.org" <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"dovgaluk@ispras.ru" <dovgaluk@ispras.ru>,
	"imammedo@redhat.com" <imammedo@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: Re: [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores
Date: Fri, 11 Oct 2019 23:15:07 +0200
Message-ID: <CAL1e-=i-dqSy7dXhs_OAtfWEcSnKccQ6QvDOGPj42oruCAxV=Q@mail.gmail.com> (raw)
In-Reply-To: <87y2xrl0ta.fsf@linaro.org>

[-- Attachment #1: Type: text/plain, Size: 3593 bytes --]

On Friday, October 11, 2019, Alex Bennée <alex.bennee@linaro.org> wrote:

>
> Aleksandar Markovic <aleksandar.m.mail@gmail.com> writes:
>
> > On Friday, October 11, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
> > wrote:
> >
> >> Hi Michael,
> >>
> >> On 9/2/19 4:01 PM, Michael Rolnik wrote:
> >>
> >>> This series of patches adds 8bit AVR cores to QEMU.
> >>> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully
> >>> tested yet.
> >>> However I was able to execute simple code with functions. e.g fibonacci
> >>> calculation.
> >>> This series of patches include a non real, sample board.
> >>> No fuses support yet. PC is set to 0 at reset.
> >>>
> >>> the patches include the following
> >>> 1. just a basic 8bit AVR CPU, without instruction decoding or
> translation
> >>> 2. CPU features which allow define the following 8bit AVR cores
> >>>       avr1
> >>>       avr2 avr25
> >>>       avr3 avr31 avr35
> >>>       avr4
> >>>       avr5 avr51
> >>>       avr6
> >>>       xmega2 xmega4 xmega5 xmega6 xmega7
> >>> 3. a definition of sample machine with SRAM, FLASH and CPU which allows
> >>> to execute simple code
> >>> 4. encoding for all AVR instructions
> >>> 5. interrupt handling
> >>> 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions
> >>> 7. a decoder which given an opcode decides what istruction it is
> >>> 8. translation of AVR instruction into TCG
> >>> 9. all features together
> >>>
> >>> [..]
> >>
> >>> Michael Rolnik (7):
> >>>    target/avr: Add outward facing interfaces and core CPU logic
> >>>    target/avr: Add instruction helpers
> >>>    target/avr: Add instruction decoding
> >>>    target/avr: Add instruction translation
> >>>    target/avr: Add example board configuration
> >>>    target/avr: Register AVR support with the rest of QEMU, the build
> >>>      system, and the MAINTAINERS file
> >>>    target/avr: Add tests
> >>>
> >>> Sarah Harris (1):
> >>>    target/avr: Add limited support for USART and 16 bit timer
> peripherals
> >>>
> >>
> >> Overall architecture patches look good, but I'd like some more time to
> >> review the hardware patches. Unfortunately I won't have time until
> November.
> >> There was a chat on IRC about your series,
> >>
> > I don't see the reason why do you initiate IRC communication on this
> topic,
> > if we have the mailing list for discussing such important issues as
> > introducing a new target (that should be definitely visible to all
> > participants).
>
> IRC is often a good way of quickly discussing something when someone is
> about (often as a tangent from another discussion). I don't think there
> is anything wrong with that as long as it's followed up on the mailing
> list.
>
>
OK, at least the series got some attention, be it on IRC or on the list. I
still find it odd that suddenly, after months and months of this series
practically sitting on the list, any suggestion couldn't first be discussed
here, so that we collectively find the best outcome. But, yes, I probably
produced much ado about nothing. I hope that this would soon result in
helping Michael complete the integration. Micheal, whatever I said
regarding patch 4, is only a suggestion - if others are fine with it, I am
fine too. Best luck to all involved! :)

Aleksandar



> >
> >> I suggested Richard we could merge patches 1-4 and 7. They are almost
> >> sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS
> >> ones).
>
> Which is was ;-)
>
> --
> Alex Bennée
>
>

[-- Attachment #2: Type: text/html, Size: 4733 bytes --]

<br><br>On Friday, October 11, 2019, Alex Bennée &lt;<a href="mailto:alex.bennee@linaro.org">alex.bennee@linaro.org</a>&gt; wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
Aleksandar Markovic &lt;<a href="mailto:aleksandar.m.mail@gmail.com">aleksandar.m.mail@gmail.com</a>&gt; writes:<br>
<br>
&gt; On Friday, October 11, 2019, Philippe Mathieu-Daudé &lt;<a href="mailto:philmd@redhat.com">philmd@redhat.com</a>&gt;<br>
&gt; wrote:<br>
&gt;<br>
&gt;&gt; Hi Michael,<br>
&gt;&gt;<br>
&gt;&gt; On 9/2/19 4:01 PM, Michael Rolnik wrote:<br>
&gt;&gt;<br>
&gt;&gt;&gt; This series of patches adds 8bit AVR cores to QEMU.<br>
&gt;&gt;&gt; All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully<br>
&gt;&gt;&gt; tested yet.<br>
&gt;&gt;&gt; However I was able to execute simple code with functions. e.g fibonacci<br>
&gt;&gt;&gt; calculation.<br>
&gt;&gt;&gt; This series of patches include a non real, sample board.<br>
&gt;&gt;&gt; No fuses support yet. PC is set to 0 at reset.<br>
&gt;&gt;&gt;<br>
&gt;&gt;&gt; the patches include the following<br>
&gt;&gt;&gt; 1. just a basic 8bit AVR CPU, without instruction decoding or translation<br>
&gt;&gt;&gt; 2. CPU features which allow define the following 8bit AVR cores<br>
&gt;&gt;&gt;       avr1<br>
&gt;&gt;&gt;       avr2 avr25<br>
&gt;&gt;&gt;       avr3 avr31 avr35<br>
&gt;&gt;&gt;       avr4<br>
&gt;&gt;&gt;       avr5 avr51<br>
&gt;&gt;&gt;       avr6<br>
&gt;&gt;&gt;       xmega2 xmega4 xmega5 xmega6 xmega7<br>
&gt;&gt;&gt; 3. a definition of sample machine with SRAM, FLASH and CPU which allows<br>
&gt;&gt;&gt; to execute simple code<br>
&gt;&gt;&gt; 4. encoding for all AVR instructions<br>
&gt;&gt;&gt; 5. interrupt handling<br>
&gt;&gt;&gt; 6. helpers for IN, OUT, SLEEP, WBR &amp; unsupported instructions<br>
&gt;&gt;&gt; 7. a decoder which given an opcode decides what istruction it is<br>
&gt;&gt;&gt; 8. translation of AVR instruction into TCG<br>
&gt;&gt;&gt; 9. all features together<br>
&gt;&gt;&gt;<br>
&gt;&gt;&gt; [..]<br>
&gt;&gt;<br>
&gt;&gt;&gt; Michael Rolnik (7):<br>
&gt;&gt;&gt;    target/avr: Add outward facing interfaces and core CPU logic<br>
&gt;&gt;&gt;    target/avr: Add instruction helpers<br>
&gt;&gt;&gt;    target/avr: Add instruction decoding<br>
&gt;&gt;&gt;    target/avr: Add instruction translation<br>
&gt;&gt;&gt;    target/avr: Add example board configuration<br>
&gt;&gt;&gt;    target/avr: Register AVR support with the rest of QEMU, the build<br>
&gt;&gt;&gt;      system, and the MAINTAINERS file<br>
&gt;&gt;&gt;    target/avr: Add tests<br>
&gt;&gt;&gt;<br>
&gt;&gt;&gt; Sarah Harris (1):<br>
&gt;&gt;&gt;    target/avr: Add limited support for USART and 16 bit timer peripherals<br>
&gt;&gt;&gt;<br>
&gt;&gt;<br>
&gt;&gt; Overall architecture patches look good, but I&#39;d like some more time to<br>
&gt;&gt; review the hardware patches. Unfortunately I won&#39;t have time until November.<br>
&gt;&gt; There was a chat on IRC about your series,<br>
&gt;&gt;<br>
&gt; I don&#39;t see the reason why do you initiate IRC communication on this topic,<br>
&gt; if we have the mailing list for discussing such important issues as<br>
&gt; introducing a new target (that should be definitely visible to all<br>
&gt; participants).<br>
<br>
IRC is often a good way of quickly discussing something when someone is<br>
about (often as a tangent from another discussion). I don&#39;t think there<br>
is anything wrong with that as long as it&#39;s followed up on the mailing<br>
list.<br>
<br></blockquote><div><br></div><div>OK, at least the series got some attention, be it on IRC or on the list. I still find it odd that suddenly, after months and months of this series practically sitting on the list, any suggestion couldn&#39;t first be discussed here, so that we collectively find the best outcome. But, yes, I probably produced much ado about nothing. I hope that this would soon result in helping Michael complete the integration. Micheal, whatever I said regarding patch 4, is only a suggestion - if others are fine with it, I am fine too. Best luck to all involved! :)</div><div><br></div><div>Aleksandar</div><div><br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
&gt;<br>
&gt;&gt; I suggested Richard we could merge patches 1-4 and 7. They are almost<br>
&gt;&gt; sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS<br>
&gt;&gt; ones).<br>
<br>
Which is was ;-)<br>
<br>
--<br>
Alex Bennée<br>
<br>
</blockquote>

  reply index

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-02 14:01 Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 1/8] target/avr: Add outward facing interfaces and core CPU logic Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 2/8] target/avr: Add instruction helpers Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 3/8] target/avr: Add instruction decoding Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 4/8] target/avr: Add instruction translation Michael Rolnik
2019-10-11 14:13   ` Aleksandar Markovic
2019-10-12 16:33     ` Michael Rolnik
2019-10-12 17:47       ` Aleksandar Markovic
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 5/8] target/avr: Add limited support for USART and 16 bit timer peripherals Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 6/8] target/avr: Add example board configuration Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 7/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file Michael Rolnik
2019-10-11 14:20   ` Eric Blake
2019-10-11 15:25   ` Philippe Mathieu-Daudé
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 8/8] target/avr: Add tests Michael Rolnik
2019-10-11 15:32 ` [PATCH v30 0/8] QEMU AVR 8 bit cores Philippe Mathieu-Daudé
2019-10-11 15:54   ` [Qemu-devel] " Aleksandar Markovic
2019-10-11 16:11     ` Alex Bennée
2019-10-11 21:15       ` Aleksandar Markovic [this message]
2019-10-11 15:41 ` Philippe Mathieu-Daudé

Reply instructions:

You may reply publically to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CAL1e-=i-dqSy7dXhs_OAtfWEcSnKccQ6QvDOGPj42oruCAxV=Q@mail.gmail.com' \
    --to=aleksandar.m.mail@gmail.com \
    --cc=alex.bennee@linaro.org \
    --cc=dovgaluk@ispras.ru \
    --cc=imammedo@redhat.com \
    --cc=mrolnik@gmail.com \
    --cc=philmd@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --cc=thuth@redhat.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

QEMU-Devel Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/qemu-devel/0 qemu-devel/git/0.git
	git clone --mirror https://lore.kernel.org/qemu-devel/1 qemu-devel/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 qemu-devel qemu-devel/ https://lore.kernel.org/qemu-devel \
		qemu-devel@nongnu.org
	public-inbox-index qemu-devel

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.nongnu.qemu-devel


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git