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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Tz9sADjW5Cx4noWIH/cQaSJzFVTbqmrE932QTIxCyuE=; b=QdyXCLNncF6gkAXVLZtvcvQuZelm8gY/M1JkFquANcqSlr3NiRmKK7i5xVaA8IZLKC hbo7rGAG4Wzuq7AhLvxAb4lU1OMBfzqJJ9lNCSxYJmzRStwVNWU1w0SD3ZEeNw1Ivt/n 6FI2q+w4G/MfwjpmpgV3LZV7mFxBMh5GDXSuLLZKfj7RN3YZilvSXAJUyGJrwcvW3RjR OERE1O1EIan2gpBrOX2DEtK7hGjhbH2RMWre8Gsh4QgLR2n4nLEh1FylUTPUboWekYug pVIPfM4EQSEHcS5g/uncfL8G0AcfeMj5qkav1ITH/1n/rmG0+HF8OyiCUOv1EME6NNes mJDg== X-Gm-Message-State: AOAM531Z1bPdn/fZzeansc0QKItfKhqv4c3n6Ydhb56f8u44L1ET6EAP wsOtDG5QP5mg5ptQuhRa/fDt5iVhSTdm602q6/YyCQ== X-Google-Smtp-Source: ABdhPJzqyNYy58j4kzdWfqLEhS8iUME7nez15p1XA/uwmF3sw4/0Y1IEH1JZRhBnOnciLPToQwRzZR4CsEXxvb0svRA= X-Received: by 2002:a67:fdc3:: with SMTP id l3mr12179417vsq.42.1636134123788; Fri, 05 Nov 2021 10:42:03 -0700 (PDT) MIME-Version: 1.0 References: <20211105031917.87837-1-imp@bsdimp.com> <20211105031917.87837-34-imp@bsdimp.com> <1fd1396f-56d6-1a60-6786-797623827dd9@linaro.org> In-Reply-To: <1fd1396f-56d6-1a60-6786-797623827dd9@linaro.org> From: Warner Losh Date: Fri, 5 Nov 2021 11:41:52 -0600 Message-ID: Subject: Re: [PATCH v4 33/36] bsd-user/arm/target_arch_signal.c: arm set_mcontext To: Richard Henderson Content-Type: multipart/alternative; boundary="00000000000041033d05d00e2905" Received-SPF: none client-ip=2607:f8b0:4864:20::92b; envelope-from=wlosh@bsdimp.com; helo=mail-ua1-x92b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stacey Son , QEMU Trivial , Kyle Evans , Michael Tokarev , Laurent Vivier , QEMU Developers , Philippe Mathieu-Daude Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --00000000000041033d05d00e2905 Content-Type: text/plain; charset="UTF-8" On Fri, Nov 5, 2021 at 10:44 AM Richard Henderson < richard.henderson@linaro.org> wrote: > On 11/4/21 11:19 PM, Warner Losh wrote: > > +/* Compare to arm/arm/exec_machdep.c set_mcontext() */ > > +abi_long set_mcontext(CPUARMState *env, target_mcontext_t *mcp, int > srflag) > > +{ > > + int err = 0; > > + const uint32_t *gr = mcp->__gregs; > > + uint32_t cpsr, ccpsr = cpsr_read(env); > > + uint32_t fpscr, mask; > > + > > + cpsr = tswap32(gr[TARGET_REG_CPSR]); > > + /* > > + * Only allow certain bits to change, reject attempted changes to > non-user > > + * bits. In addition, make sure we're headed for user mode and none > of the > > + * interrupt bits are set. > > + */ > > + if ((ccpsr & ~CPSR_USER) != (cpsr & ~CPSR_USER)) { > > + return -TARGET_EINVAL; > > + } > > + if ((cpsr & CPSR_M) != ARM_CPU_MODE_USR || > > + (cpsr & (CPSR_I | CPSR_F)) != 0) { > > + return -TARGET_EINVAL; > > + } > > + mask = cpsr & CPSR_T ? 0x1 : 0x3; > > Should add a sentence or so here, pointing to the exception return > instruction used by the > freebsd kernel, which does this masking. > Will do. > > + /* > > + * Make sure T mode matches the PC's notion of thumb mode, although > > + * FreeBSD lets the processor sort this out, so we may need remove > > + * this check, or generate a signal... > > + */ > > + if (!!(tswap32(gr[TARGET_REG_PC]) & 1) != !!(cpsr & CPSR_T)) { > > + return -TARGET_EINVAL; > > + } > > Remove this. > Gone. > > + env->regs[15] = tswap32(gr[TARGET_REG_PC] & mask); > > You wanted ~mask. > Doh! Fixed. Warner > > r~ > --00000000000041033d05d00e2905 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Fri, Nov 5, 2021 at 10:44 AM Richa= rd Henderson <richard.he= nderson@linaro.org> wrote:
On 11/4/21 11:19 PM, Warner Losh wrote:
> +/* Compare to arm/arm/exec_machdep.c set_mcontext() */
> +abi_long set_mcontext(CPUARMState *env, target_mcontext_t *mcp, int s= rflag)
> +{
> +=C2=A0 =C2=A0 int err =3D 0;
> +=C2=A0 =C2=A0 const uint32_t *gr =3D mcp->__gregs;
> +=C2=A0 =C2=A0 uint32_t cpsr, ccpsr =3D cpsr_read(env);
> +=C2=A0 =C2=A0 uint32_t fpscr, mask;
> +
> +=C2=A0 =C2=A0 cpsr =3D tswap32(gr[TARGET_REG_CPSR]);
> +=C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0* Only allow certain bits to change, reject attem= pted changes to non-user
> +=C2=A0 =C2=A0 =C2=A0* bits. In addition, make sure we're headed f= or user mode and none of the
> +=C2=A0 =C2=A0 =C2=A0* interrupt bits are set.
> +=C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 if ((ccpsr & ~CPSR_USER) !=3D (cpsr & ~CPSR_USE= R)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return -TARGET_EINVAL;
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 if ((cpsr & CPSR_M) !=3D ARM_CPU_MODE_USR ||
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 (cpsr & (CPSR_I | CPSR_F)) !=3D 0) {<= br> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return -TARGET_EINVAL;
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 mask =3D cpsr & CPSR_T ? 0x1 : 0x3;

Should add a sentence or so here, pointing to the exception return instruct= ion used by the
freebsd kernel, which does this masking.

Will do.
=C2=A0
> +=C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0* Make sure T mode matches the PC's notion of= thumb mode, although
> +=C2=A0 =C2=A0 =C2=A0* FreeBSD lets the processor sort this out, so we= may need remove
> +=C2=A0 =C2=A0 =C2=A0* this check, or generate a signal...
> +=C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 if (!!(tswap32(gr[TARGET_REG_PC]) & 1) !=3D !!(cpsr= & CPSR_T)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return -TARGET_EINVAL;
> +=C2=A0 =C2=A0 }

Remove this.

Gone.
=C2=A0
> +=C2=A0 =C2=A0 env->regs[15] =3D tswap32(gr[TARGET_REG_PC] & ma= sk);

You wanted ~mask.

Doh! Fixed.

Warner
=C2=A0

r~
--00000000000041033d05d00e2905--