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[209.85.210.182]) by smtp.gmail.com with ESMTPSA id n5sm10201674pfv.159.2021.06.26.23.51.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 26 Jun 2021 23:51:02 -0700 (PDT) Received: by mail-pf1-f182.google.com with SMTP id y4so11268821pfi.9; Sat, 26 Jun 2021 23:51:02 -0700 (PDT) X-Received: by 2002:a62:b40c:0:b029:2de:4a1e:a753 with SMTP id h12-20020a62b40c0000b02902de4a1ea753mr18962975pfn.64.1624776661891; Sat, 26 Jun 2021 23:51:01 -0700 (PDT) MIME-Version: 1.0 References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> <20210409074857.166082-5-zhiwei_liu@c-sky.com> In-Reply-To: <20210409074857.166082-5-zhiwei_liu@c-sky.com> From: Frank Chang Date: Sun, 27 Jun 2021 14:50:51 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode To: LIU Zhiwei Content-Type: multipart/alternative; boundary="000000000000c5813805c5b9cb20" Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , Alistair Francis , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000c5813805c5b9cb20 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LIU Zhiwei =E6=96=BC 2021=E5=B9=B44=E6=9C=889=E6=97= =A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:51=E5=AF=AB=E9=81=93=EF=BC=9A > The xie CSR appears hardwired to zero in CLIC mode, replaced by separate > memory-mapped interrupt enables (clicintie[i]). Writes to xie will be > ignored and will not trap (i.e., no access faults). > > Signed-off-by: LIU Zhiwei > --- > target/riscv/csr.c | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 4c31364967..74bc7a08aa 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -23,6 +23,10 @@ > #include "qemu/main-loop.h" > #include "exec/exec-all.h" > > +#if !defined(CONFIG_USER_ONLY) > +#include "hw/intc/riscv_clic.h" > +#endif > + > /* CSR function table public API */ > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) > { > @@ -611,13 +615,17 @@ static int write_mideleg(CPURISCVState *env, int > csrno, target_ulong val) > > static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) > { > - *val =3D env->mie; > + /* The xie CSR appears hardwired to zero in CLIC mode, (Section 4.3) > */ > + *val =3D riscv_clic_is_clic_mode(env) ? 0 : env->mie; > return 0; > } > > static int write_mie(CPURISCVState *env, int csrno, target_ulong val) > { > - env->mie =3D (env->mie & ~all_ints) | (val & all_ints); > + /* Writes to xie will be ignored and will not trap. (Section 4.3) */ > + if (!riscv_clic_is_clic_mode(env)) { > + env->mie =3D (env->mie & ~all_ints) | (val & all_ints); > + } > return 0; > } > > @@ -785,7 +793,8 @@ static int read_sie(CPURISCVState *env, int csrno, > target_ulong *val) > if (riscv_cpu_virt_enabled(env)) { > read_vsie(env, CSR_VSIE, val); > } else { > - *val =3D env->mie & env->mideleg; > + /* The xie CSR appears hardwired to zero in CLIC mode. (Section > 4.3) */ > + *val =3D riscv_clic_is_clic_mode(env) ? 0 : env->mie & env->mide= leg; > } > return 0; > } > @@ -805,6 +814,10 @@ static int write_sie(CPURISCVState *env, int csrno, > target_ulong val) > } else { > target_ulong newval =3D (env->mie & ~S_MODE_INTERRUPTS) | > (val & S_MODE_INTERRUPTS); > + /* Writes to xie will be ignored and will not trap. (Section 4.3= ) > */ > + if (riscv_clic_is_clic_mode(env)) { > + return 0; > + } > Minor: This one can be omitted as write_sie() will eventually call write_mie(). Anyway, Reviewed-by: Frank Chang > write_mie(env, CSR_MIE, newval); > } > > -- > 2.25.1 > > > --000000000000c5813805c5b9cb20 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
LIU Zhiwei <zhiwei_liu@c-sky.com> =E6=96=BC 2021=E5=B9=B44=E6=9C= =889=E6=97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:51=E5=AF=AB=E9=81=93= =EF=BC=9A
The xie CSR appears hardwired to zero in CLIC mode, re= placed by separate
memory-mapped interrupt enables (clicintie[i]). Writes to xie will be
ignored and will not trap (i.e., no access faults).

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
=C2=A0target/riscv/csr.c | 19 ++++++++++++++++---
=C2=A01 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4c31364967..74bc7a08aa 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -23,6 +23,10 @@
=C2=A0#include "qemu/main-loop.h"
=C2=A0#include "exec/exec-all.h"

+#if !defined(CONFIG_USER_ONLY)
+#include "hw/intc/riscv_clic.h"
+#endif
+
=C2=A0/* CSR function table public API */
=C2=A0void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
=C2=A0{
@@ -611,13 +615,17 @@ static int write_mideleg(CPURISCVState *env, int csrn= o, target_ulong val)

=C2=A0static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)=
=C2=A0{
-=C2=A0 =C2=A0 *val =3D env->mie;
+=C2=A0 =C2=A0 /* The xie CSR appears hardwired to zero in CLIC mode, (Sect= ion 4.3) */
+=C2=A0 =C2=A0 *val =3D riscv_clic_is_clic_mode(env) ? 0 : env->mie;
=C2=A0 =C2=A0 =C2=A0return 0;
=C2=A0}

=C2=A0static int write_mie(CPURISCVState *env, int csrno, target_ulong val)=
=C2=A0{
-=C2=A0 =C2=A0 env->mie =3D (env->mie & ~all_ints) | (val & a= ll_ints);
+=C2=A0 =C2=A0 /* Writes to xie will be ignored and will not trap. (Section= 4.3) */
+=C2=A0 =C2=A0 if (!riscv_clic_is_clic_mode(env)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mie =3D (env->mie & ~all_ints) = | (val & all_ints);
+=C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0return 0;
=C2=A0}

@@ -785,7 +793,8 @@ static int read_sie(CPURISCVState *env, int csrno, targ= et_ulong *val)
=C2=A0 =C2=A0 =C2=A0if (riscv_cpu_virt_enabled(env)) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0read_vsie(env, CSR_VSIE, val);
=C2=A0 =C2=A0 =C2=A0} else {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 *val =3D env->mie & env->mideleg; +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* The xie CSR appears hardwired to zero in CL= IC mode. (Section 4.3) */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 *val =3D riscv_clic_is_clic_mode(env) ? 0 : en= v->mie & env->mideleg;
=C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0return 0;
=C2=A0}
@@ -805,6 +814,10 @@ static int write_sie(CPURISCVState *env, int csrno, ta= rget_ulong val)
=C2=A0 =C2=A0 =C2=A0} else {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong newval =3D (env->mie &= ; ~S_MODE_INTERRUPTS) |
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(val & S_MODE_INTERRUPTS);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Writes to xie will be ignored and will not = trap. (Section 4.3) */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (riscv_clic_is_clic_mode(env)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }<= br>

Minor:
This one can be omitte= d as write_sie() will eventually call write_mie().

Anyway,
Reviewed-by: Frank Chang <frank.chang@sifive.com>
=C2=A0
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0write_mie(env, CSR_MIE, newval);
=C2=A0 =C2=A0 =C2=A0}

--
2.25.1


--000000000000c5813805c5b9cb20--